3D Memory Device With Bonded Peripheral Circuit Die
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Solution Overview
Problem
As three-dimensional memory devices scale down, the area occupied by peripheral logic circuitry increases, and high-temperature processing steps used in manufacturing these devices can damage the logic devices on the same substrate, leading to performance degradation.
Innovation Solution
A configuration where a peripheral circuit die containing logic devices, such as CMOS devices, is bonded to a memory die with a three-dimensional memory device, isolating the logic devices from the high-temperature processing steps, and using a monolithic three-dimensional NAND string memory device with alternating stacks of insulating and conductive layers to form memory stack structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory devices scale down to increase memory density, then memory capacity is improved, but the area occupied by peripheral logic circuitry increases and high-temperature processing damages the logic devices
Solution Approach 1:
The device is divided into two separate dies: a memory die containing the three-dimensional NAND memory stacks and a peripheral circuit die containing the logic circuitry. This segmentation allows each die to be optimized independently, enabling high-density memory scaling without compromising logic device reliability during high-temperature processing.
Solution Approach 2:
A bonding interface is introduced as an intermediary between the memory die and peripheral circuit die. This bonding interface enables electrical connection between the two dies while physically isolating the logic devices from the high-temperature processing environment during memory die fabrication.
2Manufacturing precision
If high-temperature processing steps are used to manufacture three-dimensional memory devices, then memory structure formation is improved, but logic devices on the same substrate are damaged
Solution Approach 1:
The logic circuitry is extracted from the memory die and placed on a separate peripheral circuit die. This extraction removes the logic devices from the high-temperature processing environment, allowing high-temperature steps to be applied to the memory die without causing heat damage to sensitive logic components.
Solution Approach 2:
The device is divided into two separate dies: a memory die containing the three-dimensional NAND memory stacks and a peripheral circuit die containing the logic circuitry. This segmentation allows each die to be optimized independently, enabling high-density memory scaling without compromising logic device reliability during high-temperature processing.
3Device complexity
If peripheral logic circuitry is integrated on the same substrate as memory, then device integration is improved, but the area occupied by logic circuitry increases
Solution Approach 1:
Instead of integrating logic circuitry laterally on the same substrate (increasing chip area), the logic devices are moved to a separate die that is vertically stacked above the memory die through 3D stacking technology. This dimensional transition from 2D lateral integration to 3D vertical integration reduces the footprint area while maintaining device integration.
Solution Approach 2:
The peripheral circuit die is positioned and bonded above the memory die, creating a nested vertical arrangement where the logic layer is effectively 'nested' above the memory layer. This vertical nesting reduces the overall chip area compared to lateral integration while maintaining functional integration.
Data Source
AI summary
A three-dimensional memory device includes field effect transistors located on a substrate, lower metal interconnect structures embedded in first dielectric layers and located over the substrate, a source line located over the first dielectric layers, a stepped dielectric material portion located over the first dielectric layers and including stepped surfaces, an alternating stack of insulating layers and electrically conductive layers located over the source line and contacting the stepped surfaces of the stepped dielectric material portion, and memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel. A lateral extent of the stepped dielectric material portion decreases stepwise with a vertical distance from the substrate, and lateral extents of the electrically conductive layers increase with a vertical distance from the source line.