Bonded PLD-NAND Memory Stack With Vertical Interconnects
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Solution Overview
Problem
Conventional methods for integrating NAND flash memory and programmable logic devices result in high cross-talk and signal delay, leading to increased cost and limited working frequency, while existing FPGA applications are constrained by chip area consumption and RC delay.
Innovation Solution
A semiconductor device is fabricated by bonding a programmable logic device with an array of SRAM cells and an array of NAND memory cells, utilizing short-distance vertical metal interconnects to reduce chip size and improve data transfer rates, with the programmable logic device and NAND memory integrated on a bonded chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods for integrating NAND flash memory and programmable logic devices are used, then device functionality is achieved, but cross-talk and signal delay increase leading to higher cost and limited working frequency
Solution Approach 1:
The patent transitions from conventional planar integration to three-dimensional vertical stacking, where NAND flash memory and programmable logic devices are stacked in the vertical dimension and interconnected through through-silicon vias (TSVs). This dimensional change reduces signal path length and minimizes cross-talk between components, thereby improving signal quality and enabling higher working frequencies.
Solution Approach 2:
The patent divides the integrated device into separate functional stacks: a first stack containing NAND flash memory cells and control gates, and a second stack containing programmable logic devices. These segmented stacks are interconnected through TSVs, allowing independent optimization of each functional block while reducing mutual interference and signal delay.
2Adaptability or versatility
If FPGA applications use conventional chip designs, then logic functionality is provided, but chip area consumption and RC delay constrain performance
Solution Approach 1:
The patent employs three-dimensional vertical stacking to accommodate both NAND flash memory and programmable logic devices in the vertical dimension rather than spreading them out in the planar dimension. This reduces chip area consumption while maintaining full logic functionality through the use of TSVs for vertical interconnection between stacked layers.
3Speed
If shorter interconnect distances are used to reduce chip size, then data transfer rate improves, but manufacturing complexity increases
Solution Approach 1:
The patent achieves short interconnect distances by routing connections vertically through TSVs in the z-dimension rather than horizontally across the chip plane. This vertical interconnection approach minimizes signal path length for high-speed data transfer while the modular stacked architecture helps manage manufacturing complexity through standardized integration processes.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.