Bonded Processor-DRAM Stack With Vertical Cache Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern semiconductor devices in mobile devices face challenges due to large cache sizes occupying significant chip real estate, RC delays from cache to processor core logic, and the need for bus interface units that increase chip area and introduce additional delays.
Innovation Solution
A semiconductor device with a processor core and cache integrated on a bonded chip, featuring a first semiconductor structure with a processor and SRAM and a second structure with DRAM bonded together using short-distance vertical metal interconnects, eliminating the need for peripheral metal routing and conventional through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache is implemented using conventional discrete chips with peripheral metal routing, then chip area is reduced, but RC delays increase and data transfer speed decreases
Solution Approach 1:
The patent transitions from two-dimensional peripheral metal routing to three-dimensional vertical interconnects by bonding the cache chip to the processor chip. Data transfers occur through vertical through-silicon vias and metal interconnects perpendicular to the chip planes, eliminating the need for long peripheral routing paths and reducing RC delays while maintaining compact chip footprints.
Solution Approach 2:
The patent introduces bonding interfaces with metal interconnects and through-silicon vias as intermediary structures between the processor and cache. These intermediaries provide direct electrical pathways that replace conventional peripheral metal routing, enabling faster data transfer with reduced resistance and capacitance effects.
2Reliability
If bus interface units are added to connect processor and cache, then connectivity is improved, but chip area increases and additional delays are introduced
Solution Approach 1:
The patent merges the processor and cache into a unified three-dimensional integrated structure where interconnects are formed as integral parts of the bonding interface. This integration eliminates the need for separate bus interface units, reducing chip complexity and area while providing direct connectivity between processor cores and cache memory through the vertical interconnect pathways.
3Ease of manufacture
If conventional through-silicon vias are used for vertical interconnects, then manufacturing is simplified, but RC delays increase and bandwidth is limited
Solution Approach 1:
The patent employs composite interconnect structures combining multiple materials including copper or cobalt for low-resistance conductors, tungsten for via plugs, and low-k dielectric materials for insulation. This composite approach reduces RC delays by minimizing resistance and capacitance while maintaining manufacturability through established semiconductor fabrication processes.
Solution Approach 2:
The patent optimizes interconnect parameters including reducing via diameter, minimizing via length, decreasing metal trace width, and reducing dielectric thickness. These parameter changes collectively reduce resistance and capacitance values, thereby increasing data transfer speed and bandwidth while maintaining compatibility with conventional manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances cache performance with faster data transfer, wider bandwidth, and reduced bus interface units, leading to improved processor efficiency and system speed with shorter manufacturing cycles and higher yields.
Implementation Method 1
The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.