Bonded Processor-DRAM Structure With Vertical Memory Interconnects
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Solution Overview
Problem
Modern semiconductor devices face challenges with large chip size due to the inclusion of cache and bus interface units, which increase RC delay and occupy additional chip area, limiting performance and efficiency.
Innovation Solution
Integration of a processor core, cache, and main memory on a bonded chip using short-distance vertical metal interconnects, eliminating the need for peripherally-distributed metal routing and conventional through silicon vias, with separate fabrication of SRAM and DRAM structures and direct bonding through a bonding interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processor, cache, and main memory are integrated on a single chip using conventional metal routing, then functionality is achieved, but chip size increases and RC delay worsens
Solution Approach 1:
The patent transitions from planar metal routing to three-dimensional vertical interconnects through wafer bonding. Processor and memory chips are bonded face-to-face with bonding contacts extending vertically through the bonding interface, enabling short-distance vertical data transfer paths that eliminate long peripheral metal routes and reduce RC delay while compacting chip area.
Solution Approach 2:
The system is segmented into separate processor and memory chips that are independently fabricated and then bonded together. This segmentation allows each chip to be optimized independently while the bonding interface provides direct vertical interconnection, avoiding the need for large-area metal routing across a single monolithic chip.
2Reliability
If peripherally-distributed metal routing is used to connect processor and memory, then electrical connection is achieved, but RC delay increases and bandwidth decreases
Solution Approach 1:
The patent replaces two-dimensional peripherally-distributed metal routing with three-dimensional vertical interconnects. Bonding contacts extend vertically through the wafer bonding interface, creating direct short-distance electrical pathways that eliminate long signal paths and reduce RC delay while maintaining reliable electrical connection.
3Reliability
If conventional through silicon vias are used for interchip connection, then electrical connection is achieved, but manufacturing complexity and cycle time increase
Solution Approach 1:
Bonding contacts are formed on the chip surfaces before wafer bonding occurs. This preliminary formation of interconnect structures eliminates the need for complex post-bonding through silicon via formation, reducing manufacturing steps and cycle time while ensuring reliable electrical connection through the bonding interface.
Solution Approach 2:
The patent merges the interconnect formation process with the wafer bonding process itself. Bonding contacts are formed as part of the chip fabrication before bonding, and the wafer bonding operation directly creates the electrical connection, eliminating separate via formation and filling steps required in conventional approaches.
4Adaptability or versatility
If cache and bus interface units are included on the processor chip, then functionality is improved, but chip area increases and manufacturing yield decreases
Solution Approach 1:
The patent segments the system into processor chip and memory chip, with cache and bus interface functions distributed between them. This segmentation reduces the complexity and area requirements on each individual chip, improving manufacturing yield while maintaining overall system functionality through the bonded interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip size, improves data transfer speed and efficiency, increases bandwidth, and enhances system speed with faster memory interface, while minimizing manufacturing cycle time and improving yield.
Implementation Method 1
The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.