Bonded Processor-DRAM Stack With Short Vertical Interconnects
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Solution Overview
Problem
Modern semiconductor devices face challenges with large chip size due to the integration of multiple discrete chips, such as application processors, DRAM, and controllers, which occupy significant real estate and introduce RC delays, necessitating improved integration and connectivity for faster data transfer and reduced power consumption.
Innovation Solution
A semiconductor device is fabricated with a processor core and SRAM integrated on a bonded chip, vertically connected to DRAM through short-distance vertical metal interconnects, eliminating long-distance metal routing and conventional through silicon vias, and allowing for a unified chip with reduced size and increased memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple discrete chips (application processor, DRAM, controllers) are integrated to enable various functionalities, then device functionality is improved, but chip size increases and RC delays are introduced
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacked architecture, where processor and memory components are arranged vertically across multiple layers. This dimensional change allows multiple functional chips to be integrated without increasing lateral chip area, as components are stacked one above another and connected via through-silicon vias (TSVs).
Solution Approach 2:
The integrated device is divided into separate functional layers or stacks, with processor components in one layer and memory components in another layer. This segmentation allows each component to be optimized independently while maintaining compact overall integration through vertical stacking and TSV interconnections.
2Ease of operation
If long-distance metal routing is used to connect discrete chips, then connectivity is achieved, but RC delays increase and data transfer speed decreases
Solution Approach 1:
The patent replaces long-distance lateral metal routing with short-distance vertical interconnections through TSVs. By stacking components vertically and connecting them through the substrate thickness rather than across the chip surface, the interconnect length is dramatically reduced, minimizing RC delays and enabling faster data transfer between processor and memory.
Solution Approach 2:
Through-silicon vias (TSVs) serve as intermediary vertical interconnect structures that bridge different layers and components. These TSVs provide direct electrical pathways through the substrate, replacing complex lateral metal routing networks and enabling high-speed vertical signal transmission between stacked components.
3Device complexity
If conventional through silicon vias are used for vertical interconnection, then three-dimensional integration is achieved, but manufacturing complexity and cycle time increase
Solution Approach 1:
The patent forms TSVs and performs bonding operations at the wafer level before dicing into individual devices. This preliminary action allows multiple devices to be processed and bonded simultaneously in parallel, rather than sequentially at the die level, significantly reducing overall manufacturing cycle time while achieving complex three-dimensional integration.
Solution Approach 2:
The patent combines multiple processing steps and bonding operations into a unified wafer-level process flow. By merging TSV formation, wafer bonding, and interlayer connectivity establishment into an integrated manufacturing sequence, the process achieves three-dimensional integration more efficiently than sequential die-level operations.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts and a first dielectric layer isolating the first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including second bonding contacts and a second dielectric layer isolating the second bonding contacts. The first bonding layer is bonded to the second bonding layer. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure.