Bonded Processor-NAND Memory Stack With Vertical Interconnects
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Solution Overview
Problem
Conventional methods for using embedded NAND memory in modern devices result in cross-talk and high loading on processors, with significant RC delays and increased chip area due to bus interface units, which degrade performance and efficiency.
Innovation Solution
A semiconductor device with a processor core and SRAM integrated on a bonded chip, where NAND memory is directly bonded with short-distance vertical metal interconnects, reducing or eliminating bus interface units and metal routing, and dividing cache modules into smaller regions for improved data storage and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NAND memory is directly bonded to processor with short-distance vertical metal interconnects, then data transfer speed and processing efficiency are improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor device is divided into two separate structures: a first semiconductor structure containing the processor and SRAM, and a second semiconductor structure containing the NAND memory cells. These structures are fabricated independently on separate wafers and then bonded together, allowing each to be optimized separately while achieving fast data transfer through direct vertical interconnects at the bonding interface.
Solution Approach 2:
A bonding interface with vertical metal interconnects serves as an intermediary between the processor/SRAM structure and the NAND memory structure. This bonding interface enables direct electrical connection and fast data transfer while allowing the two structures to be fabricated using different processes and then joined together.
2Area of stationary object
If bus interface units and metal routing are reduced or eliminated, then chip area is reduced, but connection reliability may deteriorate
Solution Approach 1:
Instead of using lateral metal routing across the chip surface, the patent transitions to vertical metal interconnects at the bonding interface. This dimensional change from horizontal to vertical connections reduces the area required for routing while maintaining reliable electrical connections between the processor/SRAM and NAND memory structures.
Solution Approach 2:
The patent extracts and eliminates the traditional bus interface units and extensive metal routing that would normally be required to connect NAND memory to the processor. By using direct vertical bonding interconnects, the unnecessary intermediate routing layers and interface units are removed, reducing chip area while maintaining connection functionality.
3Productivity
If cache modules are divided into smaller regions, then array efficiency is improved, but device complexity increases
Solution Approach 1:
The cache memory is divided into multiple smaller cache regions within the SRAM array on the first semiconductor structure. This segmentation improves array efficiency by allowing more targeted and efficient data access patterns. The bonding interface with vertical interconnects provides direct access to these segmented cache regions, maintaining low complexity in the connection architecture while achieving high array efficiency.
Data Source
AI summary
First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.