Bonded Vertical Schottky Memory Structure for Dense Semiconductor Arrays
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges with reduced feature size leading to inter-device interference, limited current density, and increased parasitic capacitance due to small inter-device spaces, resulting in inefficiencies and high power consumption.
Innovation Solution
A method for manufacturing semiconductor structures involving bonding substrates with implanted hydrogen layers, forming vertical Schottky diodes and memory units, and patterning semiconductor layers to create isolated diodes and memory cells, utilizing Schottky and Ohmic contacts for improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimension of devices is reduced to increase integration density, then the number of devices per chip increases, but the inter-device space becomes too small causing interference between devices
Solution Approach 1:
The patent transitions from planar device layout to vertical three-dimensional structure. By stacking multiple functional layers (buffer layer, semiconductor layer, Schottky contact, ohmic contact) vertically, the device achieves higher integration density while maintaining sufficient lateral spacing between adjacent devices, thereby eliminating inter-device interference.
Solution Approach 2:
The device is segmented into distinct functional layers with clear boundaries. The buffer layer, semiconductor layer, Schottky contact, and ohmic contact are separated and optimized independently, allowing each layer to perform its specific function without interfering with adjacent devices.
2Productivity
If the size of transistor is reduced to increase integration density, then more devices fit on chip, but the current density capability is limited by saturation region
Solution Approach 1:
The patent changes the device type from transistor to vertical Schottky diode, fundamentally altering the electrical characteristics. The Schottky contact creates a metal-semiconductor junction with different current-voltage properties, enabling higher current density operation without entering saturation region, thus maintaining power capability while achieving high integration density.
3Productivity
If the channel region of transistor is reduced to increase integration density, then device size decreases, but current leakage increases causing high power consumption
Solution Approach 1:
The patent extracts the channel region concept from transistor architecture and replaces it with a vertical diode structure. By removing the horizontal channel and replacing with vertical current path through doped semiconductor layers, the design eliminates the leakage-prone channel while maintaining compact footprint for high integration density.
Solution Approach 2:
The patent uses composite material structure with different doped regions (n-type and p-type semiconductor layers) stacked vertically. This composite structure creates multiple depletion regions that block leakage currents, reducing power consumption while maintaining small device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of smaller, high-performance Schottky diodes and memory cells with reduced power consumption and faster access times, addressing inter-device interference and current density limitations.
Implementation Method 1
The second substrate comprises a single crystalline semiconductor material and an implanted hydrogen layer
Implementation Method 2
bonding the first structure and the second structure by a bonding layer to form a bonded structure
Data Source
AI summary
The present disclosure relates to a method for manufacturing a semiconductor structure. The method comprises providing a first structure. The first structure comprises a first substrate. The method comprises providing a second structure. The second structure comprises a second substrate and a first device metal layer on and in contact with the second substrate. The second substrate comprises a single crystalline semiconductor material and an implanted hydrogen layer. The method comprises bonding the first structure and the second structure by a bonding layer to form a bonded structure. The method comprises removing a portion of the second substrate from approximately the implanted hydrogen layer to form a first semiconductor layer. The method comprises patterning the first semiconductor layer. The method comprises forming at least one of a second device metal layer and a second conductive metal layer.