Bonded Substrate Conductive Region via Ion Implantation
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Solution Overview
Problem
Conventional techniques for isolating devices on semiconductor wafers consume valuable surface area and generate non-planar surfaces, limiting integration density and device yields, and epitaxial wafers are expensive and time-consuming to produce.
Innovation Solution
A method and device for forming a conductive region between bonded substrates using an implanting technique, which includes joining substrates, removing material while maintaining attachment, implanting particles to facilitate electrical coupling, and treating the substrate to enhance crystallization and reduce bond voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation techniques (LOCOS, trench isolation) are used to isolate devices on bulk silicon wafers, then device isolation is achieved, but valuable wafer surface area is consumed and non-planar surfaces are generated, limiting integration density
Solution Approach 1:
The patent extracts the isolation function from traditional bulk silicon techniques by transferring devices to bonded substrates. The isolation structures are removed from the device fabrication process and replaced by the bonded substrate architecture itself, which provides natural isolation while preserving wafer surface area for active device placement.
Solution Approach 2:
The patent moves from two-dimensional device placement on a single wafer to three-dimensional bonding of multiple substrates. By stacking substrates and forming conductive regions through the bond interface, the invention utilizes the vertical dimension to achieve both isolation and electrical connection without consuming horizontal wafer area.
2Reliability
If trench isolation is used to isolate devices, then device isolation is achieved, but the process is extremely time consuming and difficult to achieve accurately
Solution Approach 1:
The patent removes the time-consuming trench isolation process from the fabrication sequence by using bonded substrates that provide inherent isolation. The isolation function is achieved through the substrate bonding architecture rather than through lengthy etching and filling operations.
Solution Approach 2:
The substrates are bonded together in advance with pre-formed conductive regions, eliminating the need for time-consuming isolation processes later in fabrication. The bonding process itself establishes both the isolation boundaries and the electrical connection paths.
3Reliability
If epitaxial silicon wafers are used to achieve VLSI/ULSI, then device yields and crystalline quality are improved, but the process is slow and time consuming, and equipment is expensive
Solution Approach 1:
The patent segments the high-quality crystalline layer formation from the bulk wafer fabrication. Instead of growing thick epitaxial layers on entire wafers (which is slow), the invention uses thin bonded substrate layers that provide sufficient crystalline quality for devices while enabling faster processing and lower equipment costs.
Solution Approach 2:
The patent changes the thickness parameter of the crystalline layer from thick epitaxial layers (tens of micrometers) to thin bonded substrate layers (micrometers or less). This parameter change maintains the crystalline quality benefits for device performance while dramatically reducing fabrication time and equipment requirements.
4Productivity
If bonding substrates are used to achieve large scale integration, then integration density is improved, but bond voids are generated at the interface region
Solution Approach 1:
The patent introduces conductive particles as an intermediary material at the bond interface. These particles fill the voids between bonded substrates and provide both mechanical bonding and electrical conduction, eliminating the harmful effect of bond voids while maintaining high integration density.
Solution Approach 2:
The implantation process uses ion implantation as an intermediary mechanism to deposit conductive material into the bond interface. This intermediary process transforms the problematic void space into a functional conductive region that enhances both bonding reliability and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher device yields, improved integration density, and reduced bond voids, using conventional technology without substantial equipment modifications, and is applicable to various semiconductor and non-semiconductor devices.
Implementation Method 1
A method and device for forming a conductive region between bonded substrates using an implanting technique
Implementation Method 2
treating the substrate to enhance crystallization
Data Source
AI summary
A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate.