Bonded Testing Elements for Low-Footprint Semiconductor Self-Test
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Solution Overview
Problem
Conventional self-testing circuits for semiconductor devices, particularly SoC devices, occupy significant chip area, hindering miniaturization efforts due to their complexity and footprint, and there is a need for efficient testing without increasing the device size.
Innovation Solution
A self-testing core or chip is directly bonded to a semiconductor element without adhesives, using hybrid direct bonding techniques, allowing separate manufacturing processes for the testing circuitry and active circuitry, enabling high-density testing with fine pitch contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-testing circuits are integrated into semiconductor devices, then testing functionality is achieved, but chip area increases
Solution Approach 1:
The patent divides the semiconductor device into separate functional segments: the active circuitry die and the testing circuitry die are manufactured independently and then bonded together. This segmentation allows each die to be optimized for its specific function without compromising the other, resolving the contradiction between achieving comprehensive testing functionality and maintaining minimal chip area.
Solution Approach 2:
The patent moves the testing circuitry from the traditional planar integration approach to a three-dimensional stacked architecture. By bonding the testing circuitry die to the active circuitry die vertically, the solution utilizes the vertical dimension to accommodate testing functionality without increasing the horizontal chip footprint, thereby resolving the area contradiction.
2Reliability
If testing circuitry is added to semiconductor devices, then device functionality can be verified, but manufacturing complexity increases
Solution Approach 1:
By segregating testing circuitry into a separate die, the patent simplifies the manufacturing process for each individual die. The active circuitry die can be manufactured without incorporating complex testing structures, while the testing die is专门 optimized for testing functions. This segmentation reduces the complexity burden on each manufacturing process.
Solution Approach 2:
The bonding interface between the active circuitry die and testing circuitry die acts as an intermediary that connects the two separate manufacturing processes. This intermediary layer enables functionality verification without requiring the integration of testing circuitry into the active circuitry manufacturing flow, thereby reducing overall manufacturing complexity.
3Ease of manufacture
If adhesive bonding is used to attach testing elements, then bonding is achieved, but manufacturing precision and reliability decrease
Solution Approach 1:
The patent extracts the adhesive layer from the bonding process, transitioning from adhesive bonding to direct bonding. By removing the adhesive intermediary, the bonding interface achieves higher precision and reliability through direct material-to-material contact, eliminating adhesive-related defects and variability while maintaining ease of manufacture through the direct bonding process.
Data Source
AI summary
A bonded structure for testing a semiconductor device and a method for testing semiconductor devices is disclosed. The bonded structure may comprise a testing element and one or more semiconductor element. The testing element may comprise a testing circuitry. The testing element may be bonded to a semiconductor device or embedded within a semiconductor device. The testing element may be configured to test the semiconductor device. The testing element may be configured to test a first semiconductor device to which it is bonded as well as other semiconductor devices bonded to the first semiconductor device.