Vertical Channel Memory Structure for Higher Cell Integration
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the need for ultra-expensive equipment for fine pattern formation, hindering cost-effective high performance.
Innovation Solution
A semiconductor memory device with a vertical channel transistor (VCT) design, incorporating a peripheral circuit substrate, channel patterns, word lines, capacitors, and bonding pads, which allows for increased integration and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory device is used, then manufacturing process is established, but integration is limited due to occupancy area of unit memory cell
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors. The channel extends vertically from the substrate surface, allowing multiple memory cells to be stacked in the vertical direction, thereby increasing integration density without requiring finer lateral pattern formation.
2Manufacturing precision
If ultra-expensive equipment is used for fine pattern formation, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
By moving to vertical channel transistors, the patent reduces dependence on expensive lithography equipment for creating extremely fine lateral patterns. The vertical structure allows standard fabrication equipment to achieve higher effective integration by utilizing the third dimension.
3Productivity
If vertical channel transistor is implemented, then integration is improved, but device complexity increases
Solution Approach 1:
The vertical channel transistor structure is divided into distinct functional segments: substrate, vertical channel, gate electrodes, insulating layers, and contact structures. This segmentation allows each component to be optimized independently while maintaining overall integration benefits.
Solution Approach 2:
The patent employs nested structures where gate electrodes and insulating layers are arranged concentrically around the vertical channel. Multiple gate electrodes can be stacked at different heights, creating a nested configuration that maximizes space utilization and integration density.
Data Source
AI summary
The semiconductor device includes a peripheral substrate, a peripheral element on the peripheral substrate, a peripheral wiring structure on the peripheral substrate and connected to the peripheral element, a lower bonding pad on the peripheral wiring structure, a bit line on the lower bonding pad, a bottom surface of the bit line faces the peripheral substrate, a first and second channel pattern on an upper surface of the bit line, a first word line between the first and second channel patterns, a second word line between the first and second channel patterns, a first and second capacitor on the first and second channel patterns respectively, a cell circuit wiring structure on the bottom surface of the bit line and connected to the bit line and an upper bonding pad between the cell circuit wiring structure and the lower bonding pad, the upper bonding pad contacting the lower bonding pad.