Bonded Vertical Memory Cell Structure for Dense 3D Integration
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Solution Overview
Problem
Semiconductor devices face challenges in increasing integration density and reliability due to the limitations of conventional planar transistor structures.
Innovation Solution
A semiconductor device with a vertical transistor structure is proposed, comprising stacked substrate structures connected by bonding pads, where bit lines and channels extend perpendicular to the substrate surfaces, allowing for enhanced integration and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar transistor structures are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) transistor structures. The vertical channels extend perpendicular to the substrate surface, allowing multiple channels to be stacked in the vertical direction. This dimensional change enables significantly higher integration density by utilizing the third dimension (vertical stacking) rather than only horizontal placement, thereby packing more transistors into the same footprint area.
Solution Approach 2:
The vertical transistor structure is segmented into multiple discrete components: separate gate electrodes (first gate electrode, second gate electrode), distinct channels (first vertical channel, second vertical channel), and individual bonding pads. This segmentation allows independent optimization and fabrication of each component, making the complex vertical structure manufacturable through standardized processes while achieving high integration density.
2Volume of moving object
If vertical transistor structure is adopted to increase integration density, then device volume is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by pre-forming sacrificial layers (first sacrificial layer, second sacrificial layer) before creating the vertical channels. These sacrificial layers are deposited and patterned in advance, providing templates that guide subsequent etching processes to form the vertical channels and gate structures. This preliminary preparation simplifies the overall manufacturing of complex vertical transistors by breaking down the process into manageable sequential steps.
Solution Approach 2:
Sacrificial layers serve as intermediary materials during fabrication. These temporary structures are introduced to define the geometry of vertical channels and gate electrodes during manufacturing, then selectively removed afterward. The intermediaries enable precise formation of complex vertical structures without requiring direct complex patterning, thereby easing the manufacturing process while achieving high integration density in reduced device volume.
3Quantity of substance
If multiple substrate structures are stacked to improve integration, then electrical connectivity between layers is enhanced, but bonding reliability challenges increase
Solution Approach 1:
The bonding pads are designed to perform multiple functions: they provide electrical connection between stacked substrate structures, serve as alignment features during bonding, and act as stress distribution areas. This self-service design simplifies the bonding process and enhances reliability by reducing the need for additional alignment marks or stress-management features.
Solution Approach 2:
The patent merges multiple functions into the bonding pad structure: electrical connection, mechanical bonding, and alignment reference. By combining these functions into a single integrated feature, the design simplifies the multi-layer stacking process and enhances bonding reliability, as the bonding pads serve as all-in-one connection points that simultaneously establish electrical continuity and structural integrity between substrate structures.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first substrate structure including a first substrate, first memory cells disposed on the first substrate, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively, forming a second substrate structure including a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively, and bonding the second substrate structure to the first substrate structure by bonding the first bonding pads and the second bonding pads. The first bit lines are electrically connected to the second bit lines, respectively, through the first bonding pads and the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines.