Bonded Semiconductor Via Layout for Stable Chip-to-Chip Coupling
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Solution Overview
Problem
Existing semiconductor devices with bonded semiconductor chips face challenges in efficiently integrating and connecting multiple chips, leading to potential electrical and structural weaknesses.
Innovation Solution
A semiconductor device design featuring a bonded structure where semiconductor chips are connected via vias with specific dimensions and orientations, ensuring stable electrical coupling through covalent bonding, using copper or copper alloy with barrier metals for the vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are bonded using conventional methods, then the device can be manufactured, but the electrical connection stability and reliability are insufficient
Solution Approach 1:
The patent merges the bonding process with via formation, where vias are formed to penetrate through the bonding interface between chips. This integration of via formation into the bonding process itself creates stable electrical connections while simplifying the overall manufacturing process, resolving the contradiction between reliability and ease of manufacture.
Solution Approach 2:
The patent applies preliminary action by forming vias and applying bonding materials before the actual bonding process. This preparatory step ensures that electrical connection pathways are established in advance, improving connection stability while making the bonding process more straightforward and reliable.
2Adaptability or versatility
If multiple semiconductor chips are bonded together, then the device functionality is enhanced, but the bonding interface becomes a weak point
Solution Approach 1:
The patent implements the nested doll principle by forming vias that penetrate through the bonding interface and embedding conductive materials within these vias. This nested structure of vias containing conductive materials strengthens the bonding interface while maintaining the enhanced functionality of multiple bonded chips.
Solution Approach 2:
The patent uses composite materials by combining bonding materials with conductive materials in the via structures. This composite approach creates a bonding interface that is both mechanically strong and electrically conductive, resolving the strength weakness while preserving device functionality.
3Productivity
If conventional bonding structures are used, then the manufacturing process is simple, but the electrical connection efficiency is low
Solution Approach 1:
The patent applies dimensionality change by forming vias that extend in the vertical dimension through the bonding interface, rather than relying solely on planar bonding contacts. This vertical via structure dramatically improves electrical connection efficiency by creating direct conductive pathways, while the via formation process uses standard semiconductor manufacturing techniques to manage complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the stability and efficiency of electrical connections between semiconductor chips, improving the overall performance and reliability of the semiconductor device.
Implementation Method 1
ensuring stable electrical coupling through covalent bonding
Data Source
AI summary
According to one embodiment, a device includes a first chip including a first via in a first surface; and a second chip including a second via in a second surface and overlapping the first chip in a direction perpendicular to the first surface. The first via includes a first side along a second direction parallel to the first surface, and a second side along a third direction parallel to the first surface, the second via includes a third side along the third direction and a fourth side along the second direction, a dimension of the first side is larger than a dimension of the second side, a dimension of the third side is larger than a dimension of the fourth side. The first via is in contact with the second via so that the first side intersects the third side.