Bonded-Wafer Decoupling Capacitors for IC Noise Suppression
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Solution Overview
Problem
In electrical integrated circuits (ICs), the limited available space makes it challenging to place decoupling capacitors close to the circuitry, reducing their effectiveness, as external capacitors are often used to supplement internal ones but are less effective due to their distance from the circuitry.
Innovation Solution
The integration of a decoupling capacitor onto a separate wafer that is then bonded to an electrical IC using wafer bonding, allowing the capacitor to be functionally coupled without occupying space on the IC, thereby reducing the need for external capacitors and improving their effectiveness by locating them closer to the circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are placed close to the circuitry, then noise suppression effectiveness is improved, but available real estate on the IC is limited
Solution Approach 1:
The patent divides the decoupling capacitor structure into two separate wafers: a first wafer containing the capacitor and a second wafer containing the circuitry. This segmentation allows the capacitor to be positioned close to the circuitry for effective noise suppression while occupying minimal space on the IC, as the capacitor resides on a separate bonded wafer rather than consuming planar real estate on the same chip.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration by bonding the first wafer containing the decoupling capacitor to the second wafer containing the circuitry. This vertical stacking in the third dimension enables the capacitor to be positioned immediately adjacent to the circuitry for optimal noise suppression effectiveness without competing for lateral space on the IC surface.
2Quantity of substance
If external decoupling capacitors are used to supplement internal capacitance, then sufficient capacitance is achieved, but effectiveness is reduced due to greater distance from circuitry
Solution Approach 1:
The patent merges the benefits of both internal and external decoupling capacitors by integrating a separate wafer containing a large-capacitance capacitor directly onto the IC. This combined structure provides sufficient total capacitance like external capacitors while maintaining the close proximity to circuitry that characterizes internal capacitors, thereby achieving both adequate capacitance quantity and high decoupling effectiveness.
Solution Approach 2:
The patent introduces a bonded wafer structure as an intermediary between the IC and external capacitors. This intermediate first wafer contains the decoupling capacitor and is directly bonded to the second wafer with circuitry, serving as a mediator that delivers large capacitance values while maintaining minimal distance from the circuitry, thus preserving decoupling effectiveness despite the supplemental nature of the capacitor.
3Reliability
If larger capacitance decoupling capacitors are used, then noise suppression capability is enhanced, but space requirements increase
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension by bonding the first wafer with the larger capacitance decoupling capacitor to the second wafer containing the circuitry. This three-dimensional arrangement enables the use of larger capacitance values without increasing the lateral footprint on the IC, as the capacitor occupies space on a separate bonded wafer rather than expanding the planar area of the original chip.
Solution Approach 2:
The patent segments the capacitor function onto a separate first wafer that is bonded to the second wafer containing the circuitry. This segmentation allows the decoupling capacitor to be optimized for larger capacitance values to enhance noise suppression capability, while the spatial separation onto a bonded wafer prevents this larger capacitor from increasing the space requirements of the original IC layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a larger capacitance integrated decoupling capacitor to be placed closer to the circuitry, enhancing noise suppression and reducing current spikes, with the integrated capacitor effectively connected between power rails (VDD and VSS), thus improving the overall performance of noise reduction.
Implementation Method 1
a first wafer and a second wafer are directly bonded along a wafer bond line
Data Source
AI summary
Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC.