Bonded Wafer Epitaxial Transistor Integration at High IC Density
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Solution Overview
Problem
The increasing complexity of processing semiconductor devices with decreased feature sizes due to higher IC density poses challenges in manufacturing integrated circuits, particularly in achieving reliable and efficient semiconductor device fabrication.
Innovation Solution
A method involving the formation of epitaxial layers, shallow trench isolation regions, and buried layers, followed by bonding and separation techniques, along with the use of dielectric layers and nanosecond annealing processes, to create a semiconductor device structure that allows for flexible material choices and reduced device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more aggressive design rules are implemented to increase IC density, then the density of IC devices increases, but the complexity of processing semiconductor devices increases
Solution Approach 1:
The patent divides the semiconductor fabrication process into multiple separate stages: forming sacrificial structures, depositing first and second dielectric layers, creating isolation regions, and forming channel structures in sequence. This segmentation allows each processing stage to be optimized independently, managing the overall complexity while achieving high device density through systematic multi-step fabrication
Solution Approach 2:
The patent introduces sacrificial structures and isolation regions as intermediary elements that facilitate the formation of high-density IC devices. These intermediary structures enable precise positioning and separation of transistor components, allowing aggressive design rules to be implemented without overwhelming processing complexity
2Quantity of substance
If feature sizes are decreased to achieve higher IC density, then the density increases, but the manufacturing reliability decreases
Solution Approach 1:
The patent employs parameter changes by depositing dielectric layers with different physical and chemical properties (different compositions, densities, and etch selectivities). This allows precise control over etching depths and feature dimensions, maintaining manufacturing reliability even as feature sizes decrease to achieve higher IC density
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial structures and isolation regions before creating the final transistor features. These pre-formed structures serve as templates and protective elements that guide subsequent processing steps, ensuring consistent feature dimensions and reliable manufacturing at reduced feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with improved structural integrity and reduced dimensions, facilitating the integration of different material channel regions and transistors, thereby enhancing manufacturing efficiency and device performance.
Implementation Method 1
An epitaxial layer is grown on a first region of a first wafer
Implementation Method 2
a nanosecond annealing process is performed on the resulting structure
Data Source
AI summary
A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.