Bonded Logic-Memory Wafer Stacking for Higher I/O Bandwidth
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Solution Overview
Problem
Conventional wafer structure fabrication limits the input/output bandwidth (I/O bandwidth) between logic and memory devices, hindering computational speed and data transmission capabilities, particularly in applications requiring high data handling such as wireless communication and artificial intelligence.
Innovation Solution
The fabrication of bonded wafer structures involves forming logic and memory device structures on separate wafers and bonding them to increase I/O bandwidth, specifically through the use of hybrid bonding techniques and through-silicon vias to establish electrical connections between the wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic and memory devices are integrated on the same wafer to improve manufacturing efficiency, then manufacturing complexity is reduced, but I/O bandwidth between logic and memory devices is limited
Solution Approach 1:
The patent divides the semiconductor system into separate logic devices on one wafer and memory devices on another wafer. This segmentation allows each wafer to be optimized independently while enabling higher I/O bandwidth through dedicated interconnect structures such as through-silicon vias and hybrid bonding interfaces between the separate wafers.
Solution Approach 2:
The patent transitions from planar integration on a single wafer to three-dimensional stacking of multiple wafers. By bonding logic and memory wafers together vertically with high-density interconnects, the system achieves increased I/O bandwidth while maintaining manufacturing efficiency through wafer-level processing.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements increase
Solution Approach 1:
By separating logic and memory devices onto different wafers, the patent allows each wafer to be manufactured with optimized feature sizes for its specific function. This avoids the need to reduce minimum feature size across all devices, thereby maintaining manufacturing precision while achieving high overall integration density through vertical stacking.
Data Source
AI summary
A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.