Bonded Wafer Photolithography Alignment Using Overlay Shift Compensation

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Solution Overview

Problem

In 3D IC manufacturing, misalignment between the first and second 2D IC structures due to processing tool limitations leads to short circuits and connection failures, decreasing device yield, especially as feature sizes shrink.

Innovation Solution

A method involving lower and upper alignment marks on a handle and semiconductor wafer, respectively, with an overlay measurement apparatus to measure and compensate for the overlay shift during photolithography, allowing for accurate alignment of patterned layers without optical alignment during bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photolithography alignment is performed without compensation for bonding misalignment, then processing is simpler and faster, but manufacturing precision deteriorates due to overlay shifts causing short circuits and connection failures

Engineering Contradiction:

Improvealignment precisionVSAvoidalignment process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Alignment marks are formed on both the handle wafer and the first 2D IC structure before bonding occurs. This preliminary preparation enables post-bonding alignment measurements without requiring complex real-time adjustment mechanisms during the bonding process itself.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces mechanical/optical alignment adjustment mechanisms with a measurement-and-compensation approach. Instead of using complex alignment tools during bonding, the system measures the actual overlay shift after bonding and compensates for it during photolithography, substituting mechanical precision requirements with computational correction.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If feature sizes are reduced to increase device density, then productivity improves, but manufacturing precision deteriorates as misalignment becomes more critical and causes higher defect rates

Engineering Contradiction:

Improvedevice densityVSAvoidalignment precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system measures the actual overlay shift between the handle wafer and the first 2D IC structure after bonding, then feeds this measurement information back to the photolithography tool. This feedback loop enables real-time compensation for misalignment, ensuring that even as feature sizes shrink, the alignment precision required for high-density devices is maintained.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the approach from preventing misalignment through mechanical precision to measuring and compensating for it through parameter adjustment. By adjusting photolithography parameters based on measured overlay shifts, the system maintains manufacturing precision despite reduced feature sizes and increased device density.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If optical alignment is performed during bonding to improve precision, then alignment accuracy improves, but processing time increases and costs rise

Engineering Contradiction:

Improvealignment precisionVSAvoidprocessing time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

Alignment marks are prepared in advance on both wafers, and the actual alignment measurement is performed after bonding rather than during it. This shifts the timing of precision measurement to a point where the structures are already bonded, eliminating the need for time-consuming optical alignment procedures during the bonding process itself.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent substitutes optical alignment mechanisms with a measurement-and-compensation method. Instead of using optical tools to physically align the wafers during bonding, the system measures the resulting overlay shift and compensates for it during photolithography, significantly reducing processing time while maintaining precision.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces short circuits and connection failures by ensuring precise alignment of patterned layers, thereby increasing device yield and reducing costs associated with misalignment.

Implementation Method 1

an overlay measurement apparatus is configured to measure an overlay shift between the handle wafer and the first 2D IC structure

Methodology Applied

Scientific EffectOptical detection: Light

Data Source

PatentUS11916022B2Photolithography alignment process for bonded wafers

Publication Date: 2024.02.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.