Bonded Wafer Step Structure to Prevent Edge Undercutting
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Solution Overview
Problem
The existing semiconductor manufacturing process suffers from undesirable side etching and Si edge chipping due to the use of etching solutions like HNA, which causes undercutting and structural stress at the wafer interfaces.
Innovation Solution
A wafer bonding method involving the formation of a step structure on the device wafer's back surface with an external portion higher than the inner portion, using photolithographic etching to prevent etching solution overflow and contact with the wafer interface, thereby reducing undercutting and Si edge chipping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching solution is used to perform isotropic micro-etching on the back surface of the wafer, then the damaged layer caused by grinding is removed and stress is released, but side etching occurs causing undercutting at the sidewall interface and sunken appearance
Solution Approach 1:
The patent applies local quality by creating a step structure that differentiates the back surface into two regions: an inner portion that requires etching to remove damaged layers, and an outer portion (edge region) that should be protected from etching to prevent side etching. The step structure locally modifies the surface topology, allowing the etching solution to access only the inner portion while the higher outer portion acts as a barrier, thus achieving different quality requirements in different areas of the wafer back surface.
Solution Approach 2:
The step structure is formed before the etching process as a preventive measure. By preliminarily creating the step structure with a higher outer portion, the patent prevents the etching solution from reaching the sidewall interface before side etching can occur. This preliminary structural modification ensures that when the etching solution is applied, it is naturally confined to the inner portion and cannot overflow to cause undercutting at the edges.
2Productivity
If etching solution contacts the interface between device wafer and carrier wafer, then etching can proceed, but erosion of the sidewall interface causes sunken appearance and structural stress
Solution Approach 1:
The step structure creates a local quality difference where the outer portion is elevated to form a protective barrier. This local modification ensures that the etching solution is concentrated in the inner portion where etching is needed, while the outer portion remains dry and protects the sidewall interface. The step structure thus achieves selective exposure, allowing etching efficiency in the inner region while maintaining interface integrity at the edges.
3Manufacturing precision
If the back surface is ground to remove damaged layer, then surface quality improves, but stress accumulates and requires subsequent etching
Solution Approach 1:
The step structure segments the back surface into functionally distinct zones: the inner portion that undergoes both grinding and etching to remove damaged layers and release stress, and the outer portion that is protected from etching. This segmentation allows the process to address stress removal where needed while preventing stress concentration at the edges through the protective step structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents sunken appearances and undercutting at the wafer interfaces by concentrating the etching solution on the inner portion, minimizing erosion and structural damage, thus enhancing the integrity of the bonded wafers.
Implementation Method 1
performing a thinning process with an etching solution to the inner portion of the back surface of the device wafer
Implementation Method 2
the protection structure is a photoresist
Data Source
AI summary
A wafer bonding method includes: disposing a device wafer on a carrier wafer to form an interface between the device wafer and the carrier wafer and a back surface of the device wafer opposite to the interface; forming a step structure at an upper corner of the back surface of the device wafer, so that the back surface of the device wafer has a profile of an external portion being higher than an inner portion; and performing a thinning process with an etching solution to the inner portion of the back surface of the device wafer.