Bonding Alignment Marks at the Interface for Accurate Hybrid Bonding
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Solution Overview
Problem
Conventional planar semiconductor fabrication techniques face challenges in scaling to smaller sizes, leading to increased costs and complexity, while 3D device architectures like hybrid bonding are promising but face issues with alignment accuracy and dishing effects at bonding interfaces.
Innovation Solution
The formation of bonding alignment marks directly at the bonding interface, rather than in interconnect layers, allows for direct measurement of alignment and reduces misalignment errors, using optimized marks with dimensions not exceeding 15 μm to minimize dishing effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bonding alignment marks are placed in interconnect layers away from the bonding interface, then alignment can be measured, but misalignment errors increase and measurement accuracy decreases
Solution Approach 1:
The patent extracts the alignment marks from the interconnect layers and places them directly at the bonding interface. This separation of the alignment measurement function from the interconnect structure allows for direct, accurate measurement of bonding contact alignment without the errors introduced by intermediate layer thickness variations.
Solution Approach 2:
The bonding alignment marks serve as an intermediary element at the bonding interface that mediates between the bonding contacts and the measurement process. These marks provide a direct reference for measuring alignment accuracy without being part of the electrical interconnect path, thus eliminating measurement errors.
2Ease of manufacture
If conventional planar fabrication techniques are used for scaling, then manufacturing process remains simple, but scaling to smaller sizes becomes challenging and costly
Solution Approach 1:
The patent transitions from conventional planar (2D) fabrication to 3D hybrid bonding architecture. By stacking semiconductor wafers or dies vertically and forming bonds at the bonding interface, the invention achieves higher integration density and performance while using established fabrication processes adapted for three-dimensional stacking.
3Productivity
If 3D device architecture with hybrid bonding is implemented, then density limitation is addressed and performance improves, but alignment accuracy and dishing effects become problematic
Solution Approach 1:
The patent performs preliminary alignment by placing alignment marks directly at the bonding interface before the actual bonding process. This allows for pre-measurement and correction of alignment errors, ensuring accurate bonding contact alignment while maintaining the benefits of 3D hybrid bonding architecture.
Data Source
AI summary
Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.