Bonding Connector Layout With Dummy Features for Wafer Bond Integrity
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Solution Overview
Problem
The semiconductor industry faces challenges in developing stacked semiconductor structures with improved electrical performance, particularly in achieving efficient integration density, high speed, greater bandwidth, low power consumption, and reduced latency.
Innovation Solution
The method involves forming a semiconductor structure with a tier that includes contact pads, a dielectric structure, bonding connectors, and dummy features. The bonding connectors are electrically coupled to the contact pads, and the dummy features are laterally interposed between adjacent bonding connectors, facilitating metal diffusion and grain growth during thermal annealing to form reliable metal-to-metal bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to form stacked semiconductor structures, then manufacturing process is simpler, but bonding integrity and electrical performance are insufficient
Solution Approach 1:
The patent introduces a preliminary thermal annealing step before final bonding to pre-diffuse metals and promote grain growth at the bonding interface. This preliminary action prepares the bonding surfaces in advance, ensuring better bonding integrity and electrical performance when the stacks are eventually bonded together.
Solution Approach 2:
The patent employs controlled thermal annealing processes that change temperature parameters to optimize metal diffusion and grain growth. By carefully adjusting annealing temperature and duration, the patent achieves improved bonding integrity and electrical performance without excessively complicating the manufacturing process.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but electrical performance and signal integrity deteriorate
Solution Approach 1:
The patent changes the physical and chemical parameters of the bonding interface through thermal annealing, optimizing metal diffusion and grain growth. This improves electrical performance and signal integrity even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The patent creates a composite structure at the bonding interface by promoting intermetallic compound formation and grain growth. This composite material structure at the interface enhances electrical performance and signal integrity, compensating for the effects of reduced feature sizes.
3Reliability
If thermal annealing is applied to improve metal diffusion and grain growth, then bonding integrity improves, but process time and energy consumption increase
Solution Approach 1:
The patent optimizes thermal annealing parameters (temperature, duration, atmosphere) to achieve the necessary metal diffusion and grain growth in a controlled manner. By carefully tuning these parameters, the patent improves bonding integrity while minimizing the time and energy required for the annealing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of stacked semiconductor structures by improving bonding integrity and reducing latency, while also enabling efficient integration density and low power consumption.
Implementation Method 1
dummy features are laterally interposed between adjacent bonding connectors, facilitating metal diffusion and grain growth during thermal annealing
Implementation Method 2
facilitating metal diffusion and grain growth during thermal annealing to form reliable metal-to-metal bonds
Data Source
AI summary
A manufacturing method of a semiconductor structure is provided. The method includes: forming contact pads on an interconnect structure over a semiconductor substrate; forming a dielectric material stack on the interconnect structure; forming holes and a recess in the dielectric material stack to form a dielectric structure, wherein the holes accessibly expose portions of the contact pads, and the recess is formed between adjacent two of the holes; and forming conductive materials in the holes and the recess to respectively form bonding connectors and a dummy feature. The bonding connectors land on the contact pads, and the dummy feature is isolated and substantially equidistant from adjacent two of the bonding connectors.