Bonding Interface Alignment Marks for Precise Wafer Bonding
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Solution Overview
Problem
In semiconductor device fabrication, the alignment of bonding contacts at the bonding interface is challenging due to the dishing effect and surface flatness issues, especially when bonding alignment marks are formed in interconnect layers away from the interface, making direct measurement of alignment difficult and prone to misalignment.
Innovation Solution
Forming bonding alignment marks directly in the bonding layers at the bonding interface allows for direct measurement of bonding contact alignment, reducing overlay mismatch and dishing effects by optimizing the size and layout of these marks to be no larger than 15 μm, and using lithography overlay marks for alignment control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bonding alignment marks are formed in interconnect layers away from the bonding interface, then the alignment process is simplified, but the measurement precision of bonding contact alignment deteriorates due to dishing effect and surface flatness issues
Solution Approach 1:
The patent moves the bonding alignment marks from the interconnect layers (horizontal dimension) to the bonding interface itself (vertical dimension), placing them in the same plane where actual bonding contact alignment occurs. This dimensional relocation eliminates the dishing effect interference and enables direct measurement of alignment accuracy at the bonding interface.
2Difficulty of detecting and measuring
If bonding alignment marks are made larger to improve visibility and measurement, then the ease of detection improves, but the dishing effect and surface flatness issues worsen
Solution Approach 1:
The patent optimizes the size parameter of bonding alignment marks to a specific range (1-15 μm) that balances detectability with minimal impact on surface flatness. This parameter optimization allows the marks to be sufficiently visible for measurement while being small enough to avoid significant dishing effects during the bonding process.
3Device complexity
If conventional alignment methods are used with marks in interconnect layers, then the device complexity is reduced, but the reliability of bonding contact alignment deteriorates due to misalignment risks
Solution Approach 1:
The patent replaces the indirect mechanical alignment method (using marks in interconnect layers that require multiple measurement steps) with a direct optical alignment method (using marks at the bonding interface that can be directly observed and measured). This substitution eliminates cumulative measurement errors and significantly improves alignment reliability.
Data Source
AI summary
Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.