Bonding-Interface Signal Routing for Dense 3D Memory Dies
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing memory density and reducing complexity in memory devices, particularly in 3D memory arrays, due to the increasing density and complexity of routing and interconnect structures as feature sizes decrease.
Innovation Solution
The integration of signal routing structures at the interface between control logic and memory array structures, utilizing unused areas and forming a bond pad region with signal routing structures that are vertically aligned with bond pad structures, allowing for increased feature density and reduced pitch, thereby enhancing the compactness and performance of microelectronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased, then memory density is improved, but the density and complexity of routing and interconnect structures increases
Solution Approach 1:
The patent introduces signal routing structures that extend vertically from the bonding interface into the memory array region, utilizing the vertical dimension to route signals. This allows signals to be routed through the depth of the device rather than only laterally across the surface, effectively adding a third dimension to the routing architecture and reducing lateral routing complexity.
Solution Approach 2:
The signal routing structures are nested within the bond pad region and extend into the memory array region, with conductive structures positioned between the bonding interface and the memory cells. This nested arrangement allows multiple routing functions to be integrated within a compact volume, reducing overall device complexity while maintaining high memory density.
2Area of moving object
If feature dimensions are reduced, then integration density is improved, but routing structure complexity increases
Solution Approach 1:
By extending routing structures vertically into the memory array region rather than only laterally across the surface, the patent reduces the lateral footprint of routing structures. This vertical extension allows signals to reach memory cells more directly, reducing the need for complex lateral routing networks as feature dimensions shrink.
Solution Approach 2:
The routing architecture is segmented into distinct vertical regions: bond pad structures at the bonding interface, signal routing structures extending into the memory array region, and conductive structures within the memory array. This segmentation allows each component to be optimized independently, managing complexity as feature dimensions are reduced.
Data Source
AI summary
A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.