Semiconductor Bonding Layer Patterning to Prevent Peeling and Misalignment

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Solution Overview

Problem

The semiconductor industry faces challenges in further reducing minimum feature size due to process limitations, which affects integration density and fabrication precision, leading to issues with bonding strength and alignment in wafer substrates.

Innovation Solution

A method involving the formation of a strength adjustment pattern in a bonding layer on a first wafer substrate, allowing for adjustable bonding strength by controlling the area of the pattern, which helps in bonding two wafer substrates and preventing peeling or misalignment during fabrication, using techniques like photolithography and etching or laser irradiation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but process limitations make it difficult to continue shrinking

Engineering Contradiction:
Improveintegration densityVSAvoidminimum feature size
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The bonding layer is segmented into different regions with different thicknesses - a first bonding layer region and a second bonding layer region. This segmentation allows different portions of the bonding interface to have different bonding strengths, enabling precise control over bonding characteristics without requiring further reduction of minimum feature size.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bonding layer exhibits local quality variations where the first bonding layer region has a first bonding strength and the second bonding layer region has a second bonding strength. This local differentiation in bonding strength allows optimization of bonding characteristics in specific areas without affecting the entire structure, thereby maintaining manufacturing precision while achieving high integration density.

Inventive Principle:
Principle #3Local quality

2Strength

If bonding strength is increased to prevent peeling, then wafer substrates bond more securely, but alignment precision deteriorates due to extra bonding strength

Engineering Contradiction:
Improvebonding strengthVSAvoidalignment precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The bonding interface is divided into multiple regions with different bonding strengths. The first bonding layer region provides strong bonding to prevent peeling, while the second bonding layer region provides weaker bonding that allows for precise alignment during the bonding process. This segmentation resolves the contradiction by allowing different functional requirements to be met in different spatial locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bonding strength parameter is varied across different regions of the bonding layer by controlling the thickness of the bonding material. The first bonding layer region has a greater thickness providing higher bonding strength, while the second bonding layer region has a smaller thickness providing lower bonding strength. This parameter change enables simultaneous achievement of strong bonding and precise alignment.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If uniform bonding layer thickness is used, then fabrication is simpler, but bonding strength cannot be adjusted to prevent peeling or misalignment

Engineering Contradiction:
Improvebonding layer fabricationVSAvoidbonding strength
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The bonding layer is fabricated as a segmented structure with distinct first and second bonding layer regions having different thicknesses. This segmentation enables adjustment of bonding strength in specific areas to prevent peeling and misalignment, while the overall fabrication process remains relatively simple using standard semiconductor manufacturing techniques.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The thickness parameter of the bonding layer is varied to create regions with different bonding strengths. The first bonding layer region has a greater thickness for stronger bonding, while the second bonding layer region has a smaller thickness for weaker bonding. This parameter variation allows precise control of bonding characteristics without complicating the fabrication process.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances bonding strength while maintaining fabrication precision, reducing unwanted stress and voids, and allows for efficient semiconductor chip production by adjusting the strength adjustment pattern's size without altering the bonding material or equipment, thus improving yield and reducing costs.

Implementation Method 1

The bonding material layer is patterned to form a first bonding layer having a strength adjustment pattern

Methodology Applied
Scientific EffectPhotolithography: Photography

Implementation Method 2

using techniques like photolithography and etching or laser irradiation

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 3

The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer

Methodology Applied
Scientific EffectContact bonding: Welding

Data Source

PatentUS11756924B2Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer
Publication Date: 2023.09.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11756924B2 patent drawing
  • US11756924B2 patent drawing
  • US11756924B2 patent drawing

AI summary

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.