Bonding Pad Capacitor Layout for Stacked Semiconductor Structures

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Solution Overview

Problem

The challenge of integrating multiple semiconductor structures in a compact form while maintaining efficient electrical connectivity and reducing manufacturing complexity and area usage is not adequately addressed in existing technologies.

Innovation Solution

A semiconductor device design that utilizes bonding pads to form capacitors, allowing for simplified manufacturing processes and reduced area requirements by integrating electrode bonding pads with real bonding pads and connection patterns, enabling hybrid bonding structures and metal-insulator-metal capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple semiconductor structures are stacked vertically with separate capacitor structures, then capacitance function is achieved, but device area increases and manufacturing complexity increases

Engineering Contradiction:
Improvecapacitance functionVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the capacitor electrode function with the bonding pad function by making the bonding pads serve dual purposes: electrical connection between stacked semiconductor structures and capacitor electrodes for charge storage. This integration eliminates the need for separate capacitor structures, reducing device area while maintaining capacitance functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding pads are designed to perform multiple functions simultaneously: they provide electrical connectivity between upper and lower semiconductor structures and also serve as capacitor electrodes. This multi-functionality approach allows the same structural elements to fulfill both interconnection and energy storage roles, optimizing space utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple semiconductor structures are stacked vertically with separate capacitor structures, then capacitance function is achieved, but manufacturing process complexity increases

Engineering Contradiction:
Improvecapacitance functionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the capacitor formation process with the existing bonding pad fabrication process. By using the same bonding pad structures as capacitor electrodes, the manufacturing process requires no additional steps for capacitor creation, thereby simplifying the overall manufacturing process while achieving the desired capacitance function.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If bonding pads are used exclusively for electrical connection, then electrical connectivity is achieved, but area efficiency decreases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidarea efficiency
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The bonding pads are designed to perform multiple functions simultaneously: they provide electrical connectivity between upper and lower semiconductor structures and also serve as capacitor electrodes. This multi-functionality approach allows the same structural elements to fulfill both interconnection and energy storage roles, optimizing space utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12525560B2Semiconductor device including bonding pad
Publication Date: 2026.01.13 SK HYNIX INC
  • US12525560B2 patent drawing
  • US12525560B2 patent drawing
  • US12525560B2 patent drawing

AI summary

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.