Bonding Pad Stack With Dummy Insulating Pillars Against Delamination
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Solution Overview
Problem
Delamination is a critical issue in semiconductor manufacturing and operation, caused by thermal and mechanical stresses, moisture, poor adhesion, and material incompatibility, which affects the reliability and longevity of semiconductor devices.
Innovation Solution
The introduction of dummy insulating pillars and bonding layers with offset stresses to stabilize the bonding interface, preventing delamination by replacing conventional dummy bonding vias and ensuring proper planarization during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dummy bonding vias are used during manufacturing, then planarization can be achieved, but delamination occurs due to thermal and mechanical stresses
Solution Approach 1:
The patent removes dummy bonding vias from the scribe lane region after they have served their planarization purpose. By extracting these unnecessary structures, the source of stress-induced delamination is eliminated while the beneficial planarization effect is preserved.
Solution Approach 2:
The patent introduces dummy insulating pillars in the scribe lane region to compensate for the removal of dummy bonding vias. These pillars provide structural support and stress distribution before delamination can occur, cushioning against thermal and mechanical stresses during subsequent manufacturing and operation.
2Reliability
If dummy bonding vias are removed after planarization, then delamination is prevented, but structural support may be insufficient
Solution Approach 1:
The patent introduces dummy insulating pillars as intermediary structures that replace the structural support function of removed dummy bonding vias. These pillars act as mediators, providing necessary mechanical support and stress distribution without causing delamination.
Solution Approach 2:
The patent changes the material parameter from conductive (dummy bonding vias) to insulating (dummy insulating pillars), fundamentally altering the structural characteristics while maintaining the supportive function. This parameter change eliminates the delamination issue while preserving structural integrity.
3Productivity
If multiple layers are stacked vertically to increase integration density, then space is reduced, but stress and delamination risk increase
Solution Approach 1:
The patent segments the bonding interface region into chip regions and scribe lane regions, applying different structural solutions to each. The scribe lane region receives special treatment with dummy insulating pillars to handle stress, while chip regions maintain normal bonding pad structures, enabling high integration density without compromising overall reliability.
Data Source
AI summary
A semiconductor device may include a first interlayer insulating layer; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first bonding pad disposed in the first interlayer insulating layer; a second bonding pad disposed in the second interlayer insulating layer and connected to the first bonding pad; a first bonding via penetrating through the first bonding pad; a second bonding via penetrating through the second bonding pad and connected to the first bonding via; a first dummy insulating pillar extending through the first interlayer insulating layer; and a second dummy insulating pillar extending through the second interlayer insulating layer and connected to the first dummy insulating pillar.