Bonding Pad Edge Spacers for Moisture-Safe Bump Interconnects

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Solution Overview

Problem

The miniaturization of semiconductor devices leads to increased complexity in manufacturing and integration, resulting in issues such as poor electrical interconnection, misalignment of bonding components, and moisture-induced deterioration, which affect device performance and yield.

Innovation Solution

The semiconductor device incorporates a bonding pad with a first spacer over a dielectric liner and a conductive bump, where the second spacer on the sidewall and passivation layers prevent short circuits and moisture contamination, using silicon-rich oxide layers for protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor devices are miniaturized to reduce size, then device size is reduced, but manufacturing complexity increases and reliability deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoiddevice performance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by forming edge-protecting spacers and passivation layers on the bonding pad before the bump formation process. These protective structures are prepared in advance to prevent misalignment and moisture contamination that would otherwise occur during subsequent manufacturing steps, thereby maintaining reliability despite miniaturization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses edge-protecting spacers as intermediary structures between the bonding pad and the bump. These spacers act as a protective mediator that prevents direct contact between moisture and the bonding pad interface, and also serves as a alignment reference during bump formation, thus resolving the reliability issues caused by miniaturization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If manufacturing operations are increased for integration, then device functionality is improved, but misalignment of bonding components occurs

Engineering Contradiction:
Improvedevice functionalityVSAvoidalignment of bonding components
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The edge-protecting spacers serve as intermediary alignment references during the bump formation process. By providing a physical reference structure on the bonding pad, the spacers enable precise alignment of bonding components even as the number of manufacturing operations increases for greater device functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes the visual contrast between the edge-protecting spacers and the bonding pad to facilitate alignment. The spacers create a distinct visual boundary that helps operators and automated systems align bonding components accurately, addressing the misalignment issue that arises from increased manufacturing complexity.

Inventive Principle:
Principle #32Color changes

3Volume of moving object

If device size is reduced, then miniaturization is achieved, but moisture-induced deterioration increases

Engineering Contradiction:
Improvedevice sizeVSAvoidmoisture contamination
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The passivation layer acts as an intermediary protective barrier between the bonding pad and moisture in the environment. This intermediate layer prevents moisture from directly contacting the bonding pad interface, thereby eliminating the moisture-induced deterioration problem that becomes more severe as device size is reduced.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs thin film passivation layers that conformally cover the bonding pad and edge-protecting spacers. These thin films provide effective moisture protection while maintaining the miniaturized form factor, as the films are thin enough not to significantly increase device size but sufficient to block moisture penetration.

Inventive Principle:
Principle #30Flexible shells and thin films

4Reliability

If edge-protecting structures are added to bonding pad, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the bonding pad structure into distinct functional zones: the central bonding pad area, the edge-protecting spacers, and the passivation layers. This segmentation allows each component to perform its specific function independently, improving reliability through specialized protection while keeping the overall structure organized and manageable rather than chaotic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The edge-protecting spacers serve multiple functions simultaneously: they act as alignment references for bump formation, provide physical protection to the bonding pad edges, and serve as boundaries for passivation layer deposition. This multi-functionality improves reliability without proportionally increasing complexity, as a single structure performs multiple protective and guiding roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11894328B2Semiconductor device with edge-protecting spacers over bonding pad
Publication Date: 2024.02.06 NAN YA TECH
  • US11894328B2 patent drawing
  • US11894328B2 patent drawing
  • US11894328B2 patent drawing

AI summary

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.