Semiconductor Bonding Pad Layout for Edge Misalignment Tolerance

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Solution Overview

Problem

In semiconductor manufacturing, the bonding of device dies to package substrates often results in misalignment due to the bending of edges during the pick-and-place process, leading to failed electrical connections and reduced performance and reliability of semiconductor packages.

Innovation Solution

The use of enlarged bonding pads in the edge region, which are designed to be larger than those in the central region, allows for partial contact with corresponding pads on the package substrate, mitigating misalignment issues even when pads are shifted during the pick-and-place operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard uniform bonding pads are used across the substrate, then manufacturing is simple, but misalignment occurs during pick-and-place causing failed electrical connections

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidbonding pad structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding pad structure is designed with different sizes for different locations: enlarged bonding pads in edge regions and standard bonding pads in central regions. This local differentiation addresses the specific problem of edge bending during pick-and-place while maintaining simplicity in the central area, thereby improving electrical connection reliability without uniformly increasing device complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bonding pad array is segmented into distinct regions: edge regions with enlarged bonding pads and central regions with standard bonding pads. This segmentation allows the structure to handle misalignment at edges differently from the center, improving overall connection reliability while keeping the central region simple for manufacturing.

Inventive Principle:
Principle #1Segmentation

2Reliability

If enlarged bonding pads are used in edge regions, then misalignment is mitigated, but manufacturing complexity increases

Engineering Contradiction:
Improvebonding alignment reliabilityVSAvoidbonding pad fabrication ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Enlarged bonding pads are applied locally only to edge regions where misalignment occurs during pick-and-place, rather than uniformly across the entire substrate. This localized approach improves bonding alignment reliability at critical edge positions while minimizing the overall manufacturing complexity compared to a complete redesign of all bonding pads.

Inventive Principle:
Principle #3Local quality

3Reliability

If bonding pads are made larger, then misalignment tolerance increases, but area occupied by bonding pads increases

Engineering Contradiction:
Improvebonding pad alignment toleranceVSAvoidbonding pad area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The bonding pad area is increased only in edge regions where misalignment tolerance is needed, while central regions maintain standard bonding pad sizes. This local enlargement provides the necessary alignment tolerance for reliable electrical connections at edges without unnecessarily increasing the total area occupied by bonding pads across the entire substrate.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bonding pad structure is divided into edge regions with larger area for alignment tolerance and central regions with smaller area. This segmentation ensures that area increases are concentrated only where needed for reliability, minimizing the overall area consumption while still providing sufficient misalignment tolerance at critical edge positions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240379600A1Method for forming semiconductor structure
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379600A1 patent drawing
  • US20240379600A1 patent drawing
  • US20240379600A1 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes following operations. A first substrate is provided. The first substrate includes a plurality of first bonding pads and a plurality of second bonding pads. A second substrate is provided. The second substrate includes a plurality of third bonding pads. Bonding the first bonding pads and the second bonding pads to the third bonding pads. One of the first bonding pads is separated from one of the second bonding pads by a first distance before the bonding before the bonding, and the first distance is increased to a second distance after the bonding.