Fan-Out Bonding Pad Structure to Prevent Etching and Voids
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Solution Overview
Problem
In the manufacturing of fan-out semiconductor packages, the side surface of the copper plating pattern in the bonding pad is prone to etching during seed layer etching or rework etching, leading to reliability issues and voids between the bonding pad and conductive bumps.
Innovation Solution
The semiconductor package includes bonding pads with a conductive pillar of a first diameter and a pad pattern of a second diameter greater than the first, which surrounds the protruding upper portion of the conductive pillar, preventing etching and void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-layer bonding pad structure with copper plating pattern is used, then electrical conductivity is improved, but the side surface of the copper plating pattern is exposed and prone to etching during subsequent processes
Solution Approach 1:
The bonding pad is segmented into two distinct parts: a conductive pillar (providing electrical conductivity) and a pad pattern (providing protection and bonding surface). This segmentation allows each component to fulfill its specific function without compromising the other - the conductive pillar maintains electrical connection while the pad pattern protects the copper plating from etching
Solution Approach 2:
The pad pattern acts as an intermediary layer between the copper plating pattern and the external environment. It shields the copper plating pattern from direct exposure to etching chemicals during subsequent seed layer etching or rework etching processes, thereby preventing harmful etching while maintaining electrical conductivity through the conductive pillar
2Reliability
If via holes are formed in the bonding pad, then electrical connection is established, but dimples are formed at the upper surface causing voids between the bonding pad and conductive bump
Solution Approach 1:
The bonding pad structure is divided into a conductive pillar (for electrical connection through the via hole) and a pad pattern (providing a flat upper surface). This segmentation allows the via hole to be formed for electrical connection while the pad pattern compensates for the dimple effect, providing a flat bonding surface that prevents void formation with conductive bumps
Solution Approach 2:
The solution addresses the surface topology issue by adding a new dimensional element - the pad pattern is formed on the upper surface of the conductive pillar, effectively compensating for the dimple created by the via hole. This creates a flat upper surface in the horizontal dimension despite the vertical dimension having a via hole, thereby preventing voids during bump bonding
3Reliability
If the conductive pillar diameter is smaller than the pad pattern diameter, then the pad pattern can surround and protect the conductive pillar, but the bonding pad structure becomes more complex
Solution Approach 1:
The bonding pad is segmented into two functional parts with different diameters: the conductive pillar (smaller diameter) for electrical connection and the pad pattern (larger diameter) for protection and bonding. This segmentation enables the pad pattern to surround and protect the conductive pillar while maintaining a relatively simple overall structure that can be integrated into existing semiconductor manufacturing processes
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer that includes first redistribution wirings, a protective layer that defines openings, and bonding pads that are on the protective layer and are electrically connected to the first redistribution wirings through the openings; conductive bumps that are on first bonding pads of the bonding pads; and a semiconductor chip on the first bonding pads, where each of the bonding pads includes: a conductive pillar in a respective opening of the openings of the protective layer, where the conductive pillar includes a first diameter; and a pad pattern that is on the protective layer and an upper surface of the conductive pillar, where the pad pattern includes a second diameter that is greater than the first diameter.