Bonding Pad Groove Reduces Chip Area and Prevents Cracks
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing chip area usage and preventing substrate cracks due to the placement and insulation of bonding pads, which affects the efficiency and reliability of memory cell array formation.
Innovation Solution
The semiconductor memory device incorporates a structure with alternately stacked conductive and insulation layers, memory pillars, and a bonding pad configuration that overlaps with specific regions to reduce chip area and prevent substrate cracks, utilizing hybrid bonding techniques and insulation separators to electrically insulate memory cell arrays and bonding pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are placed on the substrate surface for electrical connection, then electrical connectivity is achieved, but chip area is wasted and substrate cracks may occur
Solution Approach 1:
The bonding pad structure transitions from a two-dimensional surface placement to a three-dimensional vertical configuration by forming the bonding pad within a groove that extends into the substrate. This allows the bonding pad to occupy vertical space rather than only horizontal space, thereby reducing the chip area occupied while maintaining electrical connectivity functionality.
Solution Approach 2:
The bonding pad is nested within the groove structure, with the insulating film and bonding pad material contained inside the groove cavity. This nesting approach allows the bonding pad to be housed within the substrate volume rather than occupying additional surface area, effectively reducing the chip area requirement.
2Reliability
If bonding pads are placed on the substrate surface for electrical connection, then electrical connectivity is achieved, but substrate cracks may occur due to stress concentration
Solution Approach 1:
The insulating film is deposited on the groove bottom and sidewalls before forming the bonding pad, creating a cushioning layer that prevents direct contact between the bonding pad and the groove walls. This insulating film acts as a stress buffer, preventing stress concentration at the bonding pad-substrate interface that would otherwise lead to substrate cracks.
Solution Approach 2:
By moving the bonding pad from a surface-level position to a subsurface groove position, the structure distributes stress more effectively within the substrate volume. The groove configuration provides stress relief by allowing the bonding pad to be embedded rather than surface-mounted, reducing the likelihood of crack propagation.
3Quantity of substance
If memory cell arrays are formed with high density, then storage capacity increases, but electrical insulation between arrays becomes more difficult
Solution Approach 1:
The insulating film extends not only on the groove bottom but also on the groove sidewalls, creating a three-dimensional insulation barrier. This vertical insulation approach provides additional electrical isolation between adjacent bonding pads and memory cell arrays, enabling higher density configurations while maintaining reliable electrical insulation.
Data Source
AI summary
A semiconductor memory device includes: a stack above a peripheral circuit on a first substrate, in which first conductive layers and first insulation layers are alternately stacked in a first direction each; a first pillar through the stack, in which a semiconductor layer and each first conductive layer form a memory cell at their intersection; a second substrate including a first region above the stack and the first pillar, being connected to a semiconductor layer, and a second region juxtaposed with the first region in a second direction; a second insulation layer through the second substrate, insulating the regions from each other; and a second conductive layer including a first portion through the second substrate, and a second portion extending in the second direction above the second substrate and including a part defining a bonding pad. The second portion overlaps with the second insulation layer in the first direction.