Bonding Pad Structure With Island Portions For Chip Area Reduction
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Solution Overview
Problem
Conventional bonding pad structures in semiconductor chips are not robust enough to withstand stresses from the wire bonding process, leading to potential damage and electrical conduction failure, and they require a larger chip area due to the need to position integrated circuits away from bonding pads.
Innovation Solution
A bonding pad structure with a dielectric layer and a first metal pattern layer featuring hollowed-out patterns and island portions below the bonding pad, connected by via plugs to enhance mechanical strength and allow for signal transmission, while a second metal pattern layer further supports signal transmission and mechanical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the integrated circuit is arranged directly below the bonding pad (CUP structure), then the chip area is reduced, but the bonding pad structure becomes vulnerable to damage from wire bonding stresses
Solution Approach 1:
The bonding pad structure is segmented into multiple functional layers: a bonding pad layer at the top, a first metal pattern layer with through-holes in the middle, and a second metal pattern layer at the bottom. This segmentation allows the bonding pad to be positioned over the circuit while distributing mechanical stresses across different layers, preventing stress concentration that would damage the structure.
Solution Approach 2:
The patent implements a nested structure where the bonding pad is positioned directly over the first metal pattern layer, which in turn is positioned over the second metal pattern layer and the circuit. This nested arrangement enables the bonding pad to overlap with the circuit (reducing chip area) while maintaining structural integrity through the intermediate metal layers that act as stress buffers.
2Reliability
If the bonding pad is positioned away from the integrated circuit, then the bonding pad structure is more robust, but the chip area increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where bonding pads must be separated from circuits to a three-dimensional stacked structure. By utilizing vertical layering with multiple metal pattern layers, the bonding pad can be positioned directly over the circuit in the vertical dimension while the intermediate layers provide mechanical support and stress distribution, effectively resolving the area-reliability trade-off.
3Reliability
If via plugs are used for signal transmission in the CUP structure, then electrical connection is achieved, but stresses from wire bonding are propagated through the via plugs causing damage
Solution Approach 1:
The electrical connection path is segmented into multiple via plug layers: first via plugs connecting the bonding pad to the first metal pattern layer, and second via plugs connecting the first metal pattern layer to the second metal pattern layer. This segmentation distributes the mechanical stress from wire bonding across multiple interfaces rather than concentrating it in a single via plug structure, preventing propagation of damaging stresses.
Solution Approach 2:
The first metal pattern layer acts as an intermediary between the bonding pad and the second metal pattern layer. It provides an intermediate structural level that buffers mechanical stresses, preventing direct stress transmission from the bonding pad through the via plugs to the underlying circuit, while maintaining electrical connectivity through the via plugs.
Data Source
AI summary
A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.