Display Panel Bonding Pad Overlap for Narrow-Bezel Isolation

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Solution Overview

Problem

Current display panels with narrow bezel designs are prone to short circuits and noise interference between control circuits and fanout wiring due to the removal of planarization layers in bonding pad regions, leading to display errors and failures.

Innovation Solution

A display panel design where a planarization layer extends from the display region to the peripheral region, covering both pixel units and control circuits/wiring structures, with bonding pads formed above these layers, creating an overlapped region that avoids short circuits and signal interference while optimizing space for a narrow bezel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the planarization layer is removed in the bonding pad region to reduce non-display area, then the display region proportion increases, but short circuits between control circuit and fanout wiring occur

Engineering Contradiction:
Improvedisplay region proportionVSAvoidshort circuit prevention
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. The bonding pad is positioned above the planarization layer in the vertical dimension, while the control circuit and fanout wiring are arranged in the horizontal plane below. This spatial separation in different dimensions eliminates the short circuit risk while maximizing the display region proportion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the control circuit and fanout wiring are overlapped to reduce peripheral region area, then the narrow bezel design is achieved, but noise interference on data lines occurs

Engineering Contradiction:
Improveperipheral region areaVSAvoidnoise interference
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The control circuit is positioned in the horizontal plane within the peripheral region, while the bonding pad is elevated to the vertical dimension above the planarization layer. This three-dimensional arrangement allows the control circuit and bonding pad to overlap in the horizontal view (reducing peripheral area) while maintaining electrical isolation through the planarization layer, thus eliminating noise interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If the planarization layer is removed in the bonding pad region, then the manufacturing process is simplified, but moisture penetration from peripheral region into display region occurs

Engineering Contradiction:
Improveplanarization layer removalVSAvoidmoisture penetration
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the bonding pad from the planarization layer plane and positions it in the vertical dimension above the planarization layer. This separation allows the planarization layer to remain intact as a continuous moisture barrier across the entire substrate, including the bonding pad region, while still enabling proper electrical connections through the elevated bonding pad structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11973086B2Display panel
Publication Date: 2024.04.30 AU OPTRONICS (KUNSHAN) CO LTD
  • US11973086B2 patent drawing
  • US11973086B2 patent drawing
  • US11973086B2 patent drawing

AI summary

The invention discloses a display panel, comprising: a first substrate including a display region and a peripheral region adjacent to each other; a plurality of pixel units disposed on the first substrate and located in the display region; a control circuit disposed on the first substrate, located in the peripheral region and electrically connected to the pixel units; a planarization layer disposed on the first substrate, extending from the display region to the peripheral region and covering the pixel units and the control circuit; and a bonding pad disposed on the first substrate and located above the planarization layer; wherein a projection area of the bonding pad on the first substrate and a projection area of the control circuit on the first substrate have an overlapped region.