Semiconductor Bonding Pad Structure for Overlay Shift Tolerance

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Solution Overview

Problem

In wafer-to-wafer bonding technology, precise alignment of metal pads is required to ensure the desired surface area for electrical contact, but overlay shifts can occur, leading to increased resistance due to insufficient contact area. Additionally, the dishing effect during planarization can result in incomplete contact between metal pads, causing reliability issues.

Innovation Solution

The package structure incorporates bonding pads with a bonding surface design that includes a bonding region and at least one buffer region. This design ensures that even if overlay shift occurs, the surface area of the bonding region remains consistent, maintaining electrical resistance within acceptable limits. The buffer regions also help alleviate the dishing effect by ensuring complete contact between pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If precise alignment of metal pads is required to ensure desired surface area for electrical contact, then electrical contact quality is improved, but manufacturing complexity and difficulty increase due to overlay shift sensitivity

Engineering Contradiction:
Improveelectrical contact qualityVSAvoidalignment precision requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a buffer region surrounding the bonding region of the bonding pad. This buffer region acts as a cushion that compensates for potential overlay shifts during bonding, ensuring that even if alignment is not perfect, the bonding region maintains sufficient contact area with the corresponding pad on the other wafer, thus preserving electrical contact quality without requiring extremely precise alignment

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent modifies the geometric parameters of the bonding pad by adding a buffer region with specific dimensions (e.g., extending 1-10 micrometers beyond the bonding region). This parameter change increases the tolerance margin for alignment errors, allowing the bonding structure to maintain reliable electrical contact over a wider range of alignment conditions

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If dishing effect during planarization is present, then manufacturing process is simplified, but contact completeness between metal pads deteriorates leading to reliability issues

Engineering Contradiction:
Improveplanarization processVSAvoidcontact completeness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The buffer region serves as a cushion against the dishing effect by providing extra material that compensates for the material removal or deformation caused by dishing during planarization. This ensures that the bonding region remains fully in contact with the corresponding pad even after planarization-induced deformation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The buffer region is designed in advance to counteract the harmful dishing effect. By having this extra margin of material, the structure preemptively resists the incomplete contact that would otherwise result from dishing, maintaining reliable electrical connection

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If buffer regions are added to bonding pads to compensate for overlay shifts, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveoverlay shift toleranceVSAvoidbonding pad structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding pad is segmented into two distinct functional regions: the bonding region (for electrical contact) and the buffer region (for tolerance compensation). This segmentation allows each region to be optimized for its specific function while maintaining a relatively simple overall structure that can be fabricated using standard semiconductor manufacturing processes

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively mitigates the issues of overlay shifts and dishing effects, ensuring consistent electrical contact and improved reliability by maintaining the intended surface area of the bonding regions and preventing incomplete contact due to dishing.

Implementation Method 1

In the direct metal-to-metal bonding, two bonding pads are pressed against each other at an elevated temperature, and the inter-diffusion of the bonding pads causes the bonding of the bonding pads.

Methodology Applied
Scientific EffectDirect metal bonding: Diffusion Welding

Implementation Method 2

In the eutectic bonding, two eutectic materials are placed together, and are applied with a high pressure and a high temperature. The eutectic materials are hence molten. When the melted eutectic materials are solidified, the wafers are bonded together.

Methodology Applied
Scientific EffectEutectic bonding: Melting

Data Source

PatentUS20250070060A1Package structure and method of manufacturing the same
Publication Date: 2025.02.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250070060A1 patent drawing
  • US20250070060A1 patent drawing
  • US20250070060A1 patent drawing

AI summary

A package structure and method of manufacturing a package structure are provided. The package structure includes two semiconductor structures and two bonding layers sandwiched between both semiconductor structures. Each bonding layer has a plurality of bonding pads separated by an isolation layer. Each bonding pad has a bonding surface including a bonding region and at least one buffer region. The bonding regions in both bonding layers bond to each other. The buffer region of one semiconductor structure bonds to the isolation layer of the other semiconductor structure. Each first bonding pad has a front cross-section with a length greater than a length of a front cross-section of each second bonding pads; and each second bonding pads has a side cross-section with a length greater than a length of a front cross-section of each first bonding pad.