Bonding Pad Redistribution Layer for Wider Wire Bond Pitch

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Solution Overview

Problem

As semiconductor processing technology advances, the reduced spacing between bonding pads on integrated circuit dies leads to smaller available space for wire bonds, resulting in limitations in wire bond loop accuracy and increased electrical shorts, which lowers device yield.

Innovation Solution

A bonding pad redistribution layer is introduced, featuring additional metal layers with bonding pads at a greater pitch, allowing conductors to electrically couple first bonding pads to corresponding second bonding pads, thereby reducing wire bond shorting incidents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If feature sizes and spacing between features are reduced to enable smaller die sizes, then die size is reduced, but wire bond loop accuracy deteriorates leading to increased electrical shorts

Engineering Contradiction:
Improvedie sizeVSAvoidwire bond loop accuracy
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces an intermediate metal layer between the first bonding pad layer and the second bonding pad layer, creating a three-dimensional redistribution structure. This adds a vertical dimension to the bonding pad layout, allowing the bonding pads to be redistributed in the Z-direction while maintaining smaller planar die dimensions. The intermediate layer acts as a spatial transformer that decouples the conflicting requirements of small die size and adequate wire bond accuracy by providing additional spatial freedom in the vertical dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The intermediate metal layer serves as an intermediary structure that mediates between the first bonding pads and the second bonding pads. This intermediate layer with its bonding pads at intermediate locations provides a buffering zone that allows wire bonds to achieve larger effective pitch and improved loop accuracy, while still connecting to the densely spaced first bonding pads on the original die surface. The intermediary layer thus resolves the conflict between small die size and wire bond reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If spacing between adjacent bonding pads is reduced, then more bonding pads can be accommodated on the die, but electrical shorts between adjacent bond wires increase

Engineering Contradiction:
Improvenumber of bonding padsVSAvoidelectrical short incidence
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

By introducing an intermediate metal layer at a different vertical level, the patent enables bonding pads to be stacked in the Z-dimension. This allows a higher density of bonding pads to be accommodated on the die surface without increasing the planar spacing requirements, as pads at different vertical levels do not interfere with each other's wire bond loops, thereby maintaining reliability while increasing quantity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the intermediate metal layer with its bonding pads is embedded between the first and second bonding pad layers. This nested arrangement allows multiple generations of bonding pads to coexist in a compact vertical stack, effectively increasing the total number of bonding pads that can be accommodated within the same planar footprint while maintaining adequate spacing for reliable wire bonding at each level.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20240096826A1Apparatus and methods for bonding pad redistribution layers in integrated circuits
Publication Date: 2024.03.21 SANDISK TECHNOLOGIES LLC
  • US20240096826A1 patent drawing
  • US20240096826A1 patent drawing
  • US20240096826A1 patent drawing

AI summary

An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.