Bonding Pad Structure with Stepped Wiring Layers
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Solution Overview
Problem
The thinning of interlayer insulation and lower wiring layers in semiconductor devices due to scaling down leads to a high likelihood of cracking and peel-off defects during the wire bonding process, especially when the interlayer insulation layer, primarily made of silicon oxide, fails to adhere well to metal, causing stress and mechanical compressive forces to be unevenly distributed.
Innovation Solution
The implementation of a bonding pad structure with lower wiring layers juxtaposed within the interlayer insulation layer, where each layer's area increases in a downward direction and projects inwardly, providing a stepped configuration that reinforces the interlayer insulation layer and distributes compressive forces more evenly, preventing cracking and peel-off defects. This structure includes a series of interlayer insulation and wiring layers with progressively larger openings, ensuring a robust conductive path and reduced stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interlayer insulation layer and lower wiring layers are thinned to enable semiconductor device scaling, then device size is reduced, but the likelihood of cracking and peel-off defects increases due to poor adhesion and stress concentration
Solution Approach 1:
The bonding pad structure is segmented into multiple lower wiring layers (first, second, third lower wiring layers) with progressively larger areas, distributed throughout the interlayer insulation layer. This segmentation allows stress to be distributed across multiple discrete conductive paths rather than concentrated in a single layer, preventing crack propagation while maintaining thin overall structure for device scaling.
Solution Approach 2:
The lower wiring layers are positioned at specific locations within the interlayer insulation layer with areas that locally increase from top to bottom. This local quality variation creates regions of different mechanical properties - smaller areas near the upper wiring layer for flexibility, and larger areas near the substrate for stress distribution - optimizing both adhesion and crack resistance in different zones.
2Volume of moving object
If the interlayer insulation layer is made primarily of silicon oxide to enable thinning, then device scaling is facilitated, but adhesion to metal wiring layers deteriorates, causing peel-off defects under compressive force
Solution Approach 1:
The bonding pad structure employs a composite architecture combining silicon oxide interlayer insulation layer with multiple metal wiring layers of varying areas. The composite nature allows the silicon oxide to provide electrical insulation and mechanical support while the distributed metal wiring layers provide adhesion points and stress distribution, compensating for the inherently poor adhesion between silicon oxide and metal.
Solution Approach 2:
Instead of relying on a single thick adhesion layer, the structure segments the conductive path into multiple thinner wiring layers distributed through the insulation layer. This segmentation creates multiple adhesion interfaces between metal and silicon oxide, distributing the adhesion requirement across many small contacts rather than demanding strong adhesion across a large single interface.
3Ease of manufacture
If mechanical compressive force is applied to the bonding pad during wire bonding, then wire bonding is achieved, but stress concentration occurs at the boundary between the interlayer insulation layer and upper wiring layer, causing cracking
Solution Approach 1:
The bonding pad is segmented into multiple lower wiring layers with progressively larger areas, creating a distributed stress absorption architecture. When compressive force is applied during wire bonding, the stress is distributed across these multiple segmented conductive paths rather than concentrated at a single boundary, preventing crack initiation and propagation.
Solution Approach 2:
The lower wiring layers are arranged in a vertical dimension throughout the interlayer insulation layer thickness, creating a three-dimensional stress distribution network. This dimensional arrangement allows stress to be absorbed and distributed through the depth of the structure, rather than being confined to a two-dimensional boundary plane, thereby improving stress distribution uniformity.
Data Source
AI summary
A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.