Bonding Pad Wiring for Semiconductor Chip Area Reduction
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Solution Overview
Problem
The challenge in semiconductor apparatuses is to reduce chip size by effectively utilizing the region under the bonding pad while preventing wiring peeling or breakage due to mechanical shock during bonding, which is currently hindered by the limitations of bonding techniques and the inability to arrange fine pass-through wiring in this area.
Innovation Solution
A semiconductor apparatus with a bonding pad structure that includes a striped plug wiring pattern under the bonding pad, connected by conductive plugs made of harder materials like tungsten, which serve as anchors to prevent peeling and breakage, and maintain a pattern density similar to internal circuits, allowing for the use of fine pass-through wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lower wiring layer is disposed throughout the entire area under the bonding pad, then the bonding pad can be prevented from peeling off, but the lower wiring layer cannot be used as a signal wiring, resulting in an increase in chip size
Solution Approach 1:
The lower wiring layer under the bonding pad is segmented into multiple strip-like wiring portions arranged in parallel, rather than forming a continuous solid wiring. This segmentation allows the wiring to provide sufficient mechanical support for peeling prevention while creating open spaces that enable signal wiring functionality, thus resolving the contradiction between reliability and chip area utilization.
Solution Approach 2:
The lower wiring layer under the bonding pad is designed to serve dual functions: providing mechanical support to prevent bonding pad peeling and simultaneously functioning as a signal wiring layer. By making the wiring structure multi-functional, the patent eliminates the need for separate dedicated support structures, thereby reducing chip size while maintaining reliability.
2Area of stationary object
If a pass-through wiring is extended under the bonding pad, then the lower wiring layer can be used as a signal wiring, but the pass-through wiring may be broken due to mechanical shock during bonding
Solution Approach 1:
The strip-like wiring portions are arranged in a specific pattern with appropriate spacing and connection structures before the bonding process. This pre-arranged structure acts as a cushioning mechanism that absorbs and distributes mechanical shock during bonding, preventing wiring breakage while allowing the wiring to extend under the bonding pad for space utilization.
Solution Approach 2:
The lower wiring layer is designed with different local characteristics: strip-like portions provide mechanical strength where needed to prevent breakage, while the spaced arrangement and connection structures provide signal wiring functionality. This local differentiation of wiring properties allows the same structure to simultaneously address both reliability and area utilization requirements.
3Reliability
If a dense pattern is disposed in the region under the bonding pad, then wiring support is provided, but the pattern density is considerably different from the internal circuit portion, resulting in difficulty in determining etching or CMP conditions
Solution Approach 1:
The strip-like wiring portions are designed with specific width, spacing, and arrangement parameters that create a pattern density comparable to the internal circuit portion. By carefully controlling these geometric parameters, the patent achieves both sufficient wiring support under the bonding pad and compatibility with standard etching and CMP process conditions, eliminating the need for separate process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents wiring peeling and breakage, enables the use of fine pass-through wiring under the bonding pad, and simplifies etching and CMP processes by maintaining pattern density, thereby reducing chip size and improving diffusion yield.
Implementation Method 1
conductive plugs made of harder materials like tungsten, which serve as anchors to prevent peeling and breakage
Implementation Method 2
maintain a pattern density similar to internal circuits, allowing for the use of fine pass-through wiring
Data Source
AI summary
In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.