VCT Memory Structure with Bonding Pads and Variable-Width Vias
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the need for expensive fine pattern formation equipment, hindering cost-effective high performance and increased integration.
Innovation Solution
A semiconductor memory device with a vertical channel transistor (VCT) design that includes specific contact and bonding structures, such as cell contact structures and bonding pads, to enhance integration and reduce the width of contact vias, allowing for improved process yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional semiconductor memory device with fine pattern formation is used, then integration can be increased, but expensive equipment is required
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical channel transistors. The channel extends in the vertical direction (third direction) rather than horizontally, allowing integration increase without requiring finer two-dimensional patterns. This dimensional change enables higher density while using conventional fabrication equipment capabilities.
Solution Approach 2:
The memory device is divided into multiple stacked layers including first and second bonding pads at different heights, multiple contact via structures (first contact via, second contact via), and vertically stacked channel structures. This segmentation in the vertical direction increases integration while maintaining manufacturability through standardized repeating units.
2Reliability
If conventional contact via width is used, then manufacturing is simpler, but process yield is reduced
Solution Approach 1:
The patent employs different contact via width profiles at different locations and depths. The first contact via has a width that varies along its extension direction, being wider at the upper end and narrower at the lower end. The second contact via has a different width profile, being wider at the lower end and narrower at the upper end. These localized quality variations compensate for manufacturing tolerances and improve process yield.
Solution Approach 2:
The contact via width is intentionally varied as a parameter along the vertical direction rather than maintaining a constant width. This parameter change allows optimization of both manufacturing tolerance compensation and electrical performance, improving process yield without requiring ultra-precise uniform width control.
Data Source
AI summary
A semiconductor memory device including a peripheral circuit element disposed on a peripheral circuit substrate, a peripheral circuit contact structure connected to the peripheral circuit element, a first bonding pad disposed on the peripheral circuit contact structure, a second bonding pad disposed on the first bonding pad, an active pattern disposed on the second bonding pad, a data storage pattern disposed between the active pattern and the second bonding pad and connected to a first surface of the active pattern, a bit-line disposed on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word-line disposed on a first sidewall of the active pattern, a back gate electrode disposed on a second sidewall of the active pattern, a first cell contact structure disposed between and connecting the second bonding pad and the data storage pattern.