Chip Guard and Bonding Stack Layout for 3D Memory Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor devices deteriorates as the number of stacked memory cells increases, leading to challenges in maintaining high integration and performance.
Innovation Solution
A semiconductor device design that includes a substrate with a first connection structure, transistors, bonding structures, and a stack structure with alternately stacked insulating layers and conductive patterns, along with a channel structure and chip guard that surrounds the stack and channel structures, enhancing reliability through improved structural integrity and bonding methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacked number of memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the three-dimensional semiconductor device deteriorates
Solution Approach 1:
The device is divided into multiple independent bonding structures (first bonding structure, second bonding structure, etc.) that are stacked vertically. Each bonding structure contains bonding pads that are electrically connected through the stack, allowing the device to be segmented into functional modules that can be independently formed and bonded, thereby maintaining reliability while achieving high integration.
Solution Approach 2:
Multiple bonding structures are nested vertically one above another, with each bonding structure containing bonding pads that extend through the stack. The channel structure penetrates through multiple bonding structures, creating a nested configuration where smaller functional elements are contained within larger structural frameworks, enabling high integration without compromising operational reliability.
2Area of stationary object
If the stacked number of memory cells is increased to reduce the area occupied per unit area, then the device size is reduced, but the operational reliability deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of memory cells to a three-dimensional vertical stacking configuration. Multiple bonding structures are arranged in the vertical dimension rather than spreading out horizontally, thereby reducing the footprint area while maintaining operational reliability through proper electrical connections between stacked layers.
3Productivity
If bonding structures are stacked to achieve high integration, then the device complexity increases, but the freedom of line arrangement is improved
Solution Approach 1:
The bonding structures are designed with universal characteristics where each bonding structure contains bonding pads that can serve multiple functions: electrical connection between layers, mechanical support, and alignment references. This multi-functionality reduces the need for separate specialized structures, thereby managing complexity while achieving high integration.
Solution Approach 2:
The bonding pads within each bonding structure are positioned at specific local locations to optimize electrical connections and mechanical alignment. The channel structure penetrates through specific regions of the stacked bonding structures, creating localized functional zones that simplify the overall arrangement while maintaining high integration through precise local positioning rather than complex global routing.
Data Source
AI summary
A semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure Including a first connection conductor; a transistor disposed between the substrate and the first connection structure; a first bonding structure Including a first bonding pad connected to the first connection conductor; a second bonding structure including a second bonding pad connected to the first bonding pad; a second connection structure including a second connection conductor connected to the second bonding pad; a stack structure disposed on the second connection structure; a channel structure penetrating the stack structure; and a chip guard penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip guard surrounding the stack structure and the channel structure.