Double-Sided Bonding Substrate With Multi-Metal Ultrasonic Connectors
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Solution Overview
Problem
Semiconductor packages face challenges with structural reliability due to height adjustment issues between substrates and metal spacers, leading to defects like chip cracks and substrate cracks caused by Coefficient of Thermal Expansion (CTE) differences, and the high cost of materials with matching CTE.
Innovation Solution
The use of connecting members with different metal layers, ultrasonic bonded to substrates using an ultrasonic bonding device, which minimizes vertical distance tolerance and reduces structural stress by employing layers with varying CTE, including metals like Mo and Mn, and forming micro gaps for enhanced bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal spacers or metal posts are used for height adjustment between substrates, then structural support is provided, but height adjustment is difficult and defects such as chip cracks or substrate cracks are generated due to CTE difference and thickness tolerance
Solution Approach 1:
The connecting member is divided into multiple layers with different materials (first connecting member layer, second connecting member layer, third connecting member layer) having different CTE values. This segmentation allows each layer to contribute differently to stress distribution and height adjustment, improving both reliability and manufacturing precision.
Solution Approach 2:
The patent uses composite material structure where connecting members are formed by stacking multiple layers of different materials (e.g., Cu, Mo, W, Al) with different CTE values. This composite structure enables simultaneous achievement of structural support, height adjustment, and stress reduction during molding.
2Reliability
If material with CTE similar to semiconductor chips is used to minimize CTE difference, then structural stress is reduced, but the material is considerably expensive
Solution Approach 1:
Different layers of the connecting member have different local qualities (different CTE values) matched to different requirements. The first layer (e.g., Cu) provides electrical conductivity and basic structural support, the second layer (e.g., Mo or W) provides CTE matching to reduce stress, and the third layer (e.g., Al) provides additional stress relief. This local differentiation achieves structural stability without uniformly using expensive materials throughout.
Solution Approach 2:
The patent changes the CTE parameter distribution across different layers of the connecting member. By selecting materials with progressively different CTE values for each layer, the structure can accommodate thermal expansion differences between substrates and semiconductor chips, reducing structural stress while using cost-effective material combinations rather than uniformly expensive CTE-matched materials.
3Reliability
If solder or Ag or Cu based sinter is used for bonding, then bonding between substrates and conductors is achieved, but tolerance for vertically separated distance is not minimized
Solution Approach 1:
The connecting member structure provides dynamic adjustment capability through its multi-layer composition. The different CTE layers can dynamically compensate for vertical distance variations during bonding and subsequent thermal cycles, maintaining reliable electrical and structural connections while accommodating tolerance variations in the vertically separated distance between substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves structural stability and reduces manufacturing stress by stabilizing the bonding structure between substrates and semiconductor chips, while also lowering costs by using cost-effective materials.
Implementation Method 1
connecting members which comprises at least two layers formed of each different metal and is structurally or electrically ultrasonic bonded to the upper substrate or the lower substrate by using an ultrasonic bonding device
Data Source
AI summary
Provided is a bonding substrate, a semiconductor package having a double-sided substrate, a method of manufacturing the bonding substrate, and a method of manufacturing the semiconductor package having a double-sided substrate, wherein the bonding substrate includes at least one upper substrate; at least one lower substrate which faces and is spaced apart from the upper substrate by a regular distance; and connecting members which comprises at least two layers formed of each different metal and is structurally or electrically ultrasonic bonded to the upper substrate or the lower substrate by using an ultrasonic bonding device. Accordingly, a tolerance for a vertically separated distance between upper and lower substrates may be minimized through ultrasonic bonding between the substrate and the connecting member and structural stress generated while molding may be reduced by using connecting members having each different Coefficient of Thermal Expansion (CTE).