Semiconductor Package Bonding Wire Branch Structure
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Solution Overview
Problem
As the number of vertically stacked semiconductor dies in packages increases, the length of bonding wires also increases, leading to degradation of electrical characteristics of data signals transmitted through these wires.
Innovation Solution
The semiconductor package design includes a die stack with multiple sub-stacks connected by signal wires, interpose wires, and shielding wires, with signal extension wires connecting the sub-stacks to an interface chip, allowing independent control of each sub-stack and reducing electromagnetic interference through strategically placed shielding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked semiconductor dies is increased, then the capacity and density of the semiconductor package are improved, but the length of bonding wires increases leading to degradation of electrical characteristics
Solution Approach 1:
The patent divides the die stack into multiple sub-stacks (first sub-stack and second sub-stack) that can be independently controlled. Each sub-stack has its own signal wires connecting to the interface chip, reducing the effective wire length for signal transmission compared to a single long wire spanning all dies. This segmentation allows independent control and reduces signal degradation.
Solution Approach 2:
The patent introduces an interface chip as an intermediary component between the die stack and the external environment. The interface chip receives signals from multiple sub-stacks and can process, buffer, or regenerate signals, thereby compensating for signal degradation over long wire lengths and maintaining electrical characteristics.
2Productivity
If the length of bonding wires is increased to accommodate more stacked dies, then the capacity is improved, but signal noise and electromagnetic interference increase
Solution Approach 1:
The interface chip serves as a mediator that can actively manage signal integrity. It can include signal processing circuits, equalization circuits, or error correction mechanisms that mitigate the effects of noise and electromagnetic interference accumulated over long wire lengths.
Solution Approach 2:
By segmenting the die stack into multiple independently controllable sub-stacks, the patent reduces the maximum signal transmission distance for any single wire. Each sub-stack's signals travel shorter distances to the interface chip, reducing exposure to electromagnetic interference and signal noise.
Data Source
AI summary
A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.