Semiconductor Bonding Wire Layout for Compact Power Modules
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Solution Overview
Problem
Current power semiconductor modules face challenges in miniaturization due to limitations in bonding wire geometry, which leads to difficulties in reducing the size of the module effectively, particularly because the existing bonding wire configurations result in collisions during the bonding process, hindering further miniaturization efforts.
Innovation Solution
The semiconductor device employs a bonding wire configuration with a first bond portion connected to a semiconductor chip's electrode, an intermediate loop portion extending in a specific direction, and a second bond portion connected to a second metal layer, where the angle between the second bond portion and the wall surface is smaller than the angle of the intermediate portion, preventing collisions and allowing for reduced module size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional bonding wire configuration is used, then bonding process is simple, but bonding head collisions occur and module size cannot be reduced
Solution Approach 1:
The bonding wire is divided into three distinct portions: a first bond portion, an intermediate portion, and a second bond portion. Each portion serves a specific function and can be independently optimized. The intermediate portion acts as a spacer that prevents collision between the bonding head and the wall surface, enabling miniaturization without compromising the bonding process.
Solution Approach 2:
The intermediate portion of the bonding wire functions as an intermediary element between the first bond portion and the second bond portion. It extends in a direction away from the wall surface and maintains a distance that prevents the bonding head from colliding with the wall surface during the bonding process, thus enabling miniaturization of the module.
2Volume of moving object
If bonding wire extends close to wall surface, then module size is reduced, but bonding head collides with wall surface
Solution Approach 1:
The intermediate portion is designed in advance with a specific length and orientation that pre-establishes the necessary clearance between the bonding head and the wall surface. This preliminary geometric configuration ensures that during subsequent bonding operations, the bonding head will not collide with the wall surface, maintaining process reliability while enabling compact module design.
3Reliability
If intermediate portion extends far from wall surface, then collision is prevented, but module size increases
Solution Approach 1:
The geometric parameters of the intermediate portion, including its length, width, and orientation angle relative to the wall surface, are optimized to achieve the minimum necessary distance for collision prevention. By carefully controlling these parameters, the design prevents bonding head collisions while minimizing the space occupied by the intermediate portion, thus enabling module miniaturization.
Data Source
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AI summary
A semiconductor device according to the embodiment includes: a frame body (10) having a wall surface (10a); an insulating substrate (30) surrounded by the frame body (10), the insulating substrate (30) having a first metal layer (31) and a second metal layer (32) on a surface, the second metal layer (32) being located between the first metal layer (31) and the wall surface(10a); a semiconductor chip (38) including an electrode (38a) and provided on the first metal layer (31); and a bonding wire (41) having a first bond portion (41a) connected to the electrode (38a), a second bond portion (41b) connected to the second metal layer (32), and an intermediate portion (41c) between the first bond portion (41a) and the second bond portion (41b); wherein a second angle (Θ2) formed between a second direction in which the second bond portion (41b) extends and the wall surface (10a) is smaller than a first angler (Θ1) formed between a first direction in which the intermediate portion (41c) extends and the wall surface (10a).