Bonding Wire Inductance Balancing in High Frequency Semiconductor Devices
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Solution Overview
Problem
High frequency semiconductor devices face issues with phase matching and gain degradation due to uneven inductance distribution among input bonding wires, leading to oscillations and reduced output power.
Innovation Solution
Adjusting the length of input and output bonding wires to uniform inductance distribution by making edge wires longer than central wires, thereby minimizing mutual inductance effects and phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bonding wires are placed in parallel to increase current capacity and reduce inductance, then current capacity increases, but mutual inductance between adjacent wires causes uneven inductance distribution and phase shift
Solution Approach 1:
The patent applies local quality by making bonding wires at edge parts longer than those at central parts. This creates a non-uniform structure where each wire's length is specifically tailored to its position, compensating for the varying mutual inductance effects. Edge wires experience less mutual inductance and are made longer to increase their inductance, while central wires experience more mutual inductance and are kept shorter, achieving uniform total inductance across all parallel wires.
2Area of stationary object
If bonding wires are placed closer together to reduce area, then device area decreases, but mutual inductance increases causing greater inductance variation
Solution Approach 1:
The patent makes bonding wires at edge parts longer than those at central parts to compensate for the varying mutual inductance effects. This local differentiation in wire length ensures that despite the close spacing required for compact area, each wire achieves approximately equal total inductance, maintaining phase uniformity across all FET cells.
3Ease of manufacture
If all bonding wires are made the same length, then manufacturing is simplified, but inductance distribution becomes uneven due to mutual inductance effects
Solution Approach 1:
The patent implements local quality by differentiating bonding wire lengths based on position: edge wires are made longer while central wires are kept shorter. This resolves the contradiction by sacrificing the simplicity of uniform wire lengths to achieve the more critical goal of uniform inductance distribution and phase matching across all parallel bonding wires.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal phase matching, improves gain and output power, and suppresses oscillations by balancing the operation of each FET cell.
Implementation Method 1
each inductance becomes large because of the mutual inductance occurred between the approaching bonding wires, i.e., coupling
Data Source
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AI summary
A high frequency semiconductor device (25) includes: a field effect transistor (24) including gate terminal electrodes (G1-G10), source terminal electrodes (S1-S11), and a drain terminal electrode (D); an input circuit pattern (17) and an output circuit pattern (18) which are disposed adjoining of the field effect transistor; a plurality of input bonding wires (12,12L) configured to connect the plurality of the gate terminal electrodes (G1-G10) and the input circuit pattern (17); and a plurality of output bonding wires (14,14L) configured to connect the drain terminal electrode (D) and the output circuit pattern (18), whereby the input/output signal phase is matched by adjusting an inductance distribution of a plurality of input/output bonding wires, and whereby gain and output power is improved, and whereby an oscillation due to unbalanced operation of each FET cell is supressed.