Bondwire Integrity Testing via Parasitic Diode Signatures
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Solution Overview
Problem
Existing bondwire integrity testing methods for packaged ICs are inadequate, particularly after encapsulation, as they are either non-electrically based and imprecise or electrically based but insensitive due to reliance on conventional external resistors and fixed test limits, leading to potential failures from undetected high bondwire resistance.
Innovation Solution
The method involves applying current or voltage to forward bias parasitic diodes at each pin of a packaged IC, measuring resulting pin voltages or currents, and comparing these to stored pin-pin relationship data to identify deviations indicative of bondwire integrity issues, using a diode signature key that accounts for normal substrate and diode resistances to detect abnormal bondwire resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ESD cell testing with fixed test limits is used, then testing coverage is achieved, but measurement precision deteriorates due to wide test limits rendering the method insensitive
Solution Approach 1:
The patent changes the testing parameters from conventional fixed limits to dynamic pin-pin relationship-based limits. Instead of using fixed threshold values, the system measures relationships between multiple pins and establishes test limits based on the statistical distribution of these relationships, thereby improving measurement precision while maintaining manageable device complexity
Solution Approach 2:
The patent introduces pin-pin relationships as an intermediary measurement approach. Rather than directly measuring bondwire resistance with fixed limits, the system measures voltage relationships between multiple pins and uses these intermediate measurements to infer bondwire integrity, achieving higher sensitivity without excessive complexity
2Reliability
If copper bondwires are used instead of gold bondwires, then cost is reduced and smaller diameters are achievable, but reliability deteriorates due to increased risk of bondwire-related defects and continuity failures
Solution Approach 1:
The patent applies preliminary testing action by implementing bondwire integrity testing as part of the final package test process. This preliminary detection of potential failures allows for early identification of copper bondwire issues before they cause product failures in the field, thereby improving reliability without increasing manufacturing cost
Solution Approach 2:
The patent implements feedback through the measurement and comparison of pin-pin relationships against established limits. The system provides feedback on bondwire integrity by comparing measured relationships to expected ranges, enabling detection of copper bondwire defects and allowing for process improvement while maintaining cost-effectiveness
3Measurement precision
If non-electrically-based testing methods are used after encapsulation, then visual inspection is possible, but measurement precision deteriorates due to unclear X-ray images and slow manual inspection
Solution Approach 1:
The patent replaces mechanical/optical inspection methods (X-ray imaging and visual inspection) with electrical measurement methods. By substituting electrical measurements for optical inspection, the system achieves both high measurement precision through voltage relationship analysis and high productivity through automated electrical testing, eliminating the trade-off between accuracy and speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a sensitive and accurate method for identifying bondwire integrity problems, reducing the risk of future failures by distinguishing abnormal substrate and diode resistances from bondwire resistances, thus enhancing the reliability of packaged ICs.
Implementation Method 1
A small amount of current is provided 'backwards' to a VSS pin from signal pins being bondwire integrity tested. The current is used to forward bias the diode coupled between the signal pin and the VSS pin.
Data Source
AI summary
A method of bondwire integrity testing a packaged IC includes forcing a pin current or pin voltage level sufficient to forward bias a parasitic diode at a plurality of pins relative to a selected reference pin. The pins are connected to bond pads (BPs) on the IC by a bondwire. The bond pads coupled to a diffusion of a first type that forms the parasitic diode (D) with a region doped the second type coupled to a bondpad wirebonded to the reference pin. The resulting pin voltages or pin currents at measured, and present pin-pin relationships are determined. The present pin-pin relationships are compared to stored pin-pin relationship data for a device design of the IC. Results from the comparing are used to determine whether any present pin-pin relationships are significantly different as compared to the stored pin-pin relationships to identify a bondwire problem for at least one pin.