Bump-on-Narrow-Pad Interconnect for High Routing Density
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Solution Overview
Problem
Conventional flipchip interconnection technologies face limitations in achieving high routing density due to the large size of capture pads and the need for multiple metal layers in substrates, which increases costs and introduces electrical parasitics, limiting the efficiency and performance of semiconductor devices.
Innovation Solution
The development of a bump-on-narrow-pad (BONP) interconnect architecture, where the width of the interconnect site is less than 80% of the contact interface with the contact pad, allowing for finer interconnection geometry and elimination of vias and stubs, enabling higher routing density and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capture pads are used for flipchip interconnection, then reliable electrical connection is achieved, but routing density is limited due to large pad size
Solution Approach 1:
The patent changes the dimensional parameters of the interconnect site, reducing its width to less than 80% of the contact pad width. This parameter change enables higher routing density while maintaining reliable electrical connection through the bump structure.
Solution Approach 2:
The patent transitions from a two-dimensional pad-based interconnection to a three-dimensional bump-on-narrow-pad structure. The vertical bump component provides the electrical connection, allowing the horizontal pad width to be reduced for higher routing density.
2Adaptability or versatility
If multiple metal layers are used in substrate for routing, then comprehensive interconnection is achieved, but substrate cost increases and electrical parasitics are introduced
Solution Approach 1:
The patent extracts the routing function from multiple metal layers and consolidates it into a single metal layer. The narrow pad design allows signal traces to be formed in one layer without requiring complex multi-layer routing structures.
Solution Approach 2:
Instead of using multiple layers to achieve routing density, the patent inverts the approach by using a single layer with narrow pads that accommodate high-density routing. This reverses the conventional wisdom that more layers are needed for more complex routing.
3Ease of manufacture
If conventional interconnect site width is used, then manufacturing simplicity is maintained, but routing density and signal transmission efficiency are limited
Solution Approach 1:
The patent modifies the width parameter of the interconnect site to be less than 80% of the contact pad width. This parameter change enables finer interconnection geometry and higher routing density while remaining compatible with standard manufacturing processes.
Data Source
AI summary
A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.