Bookended Link Training Using FEC Padding Bits for DSP Coordination
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Solution Overview
Problem
Existing digital signal processor (DSP) systems face challenges in efficiently communicating signal parameters across mirrored links, particularly in adjusting power levels, performing digital pre-distortion calibration, bit error rate testing, and time synchronization, which are crucial for optimal performance but often not adequately addressed.
Innovation Solution
Implementing a system where DSPs in mirrored links communicate using forward error correction (FEC) padding bits or reserved bits to facilitate power adjustment, digital pre-distortion calibration, bit error rate testing, and time synchronization, utilizing active electrical or optical cables for connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional communication methods are used between DSPs in mirrored links, then basic signal transmission is achieved, but efficient communication of signal parameters for power adjustment, calibration, and synchronization is not achieved
Solution Approach 1:
The patent extracts signal parameter information from the existing data stream by utilizing unused FEC padding bits and reserved bits. Instead of adding separate communication channels, the invention extracts and embeds control information (power adjustment, calibration data, synchronization signals) within the existing communication framework, thereby improving communication efficiency without adding system complexity
Solution Approach 2:
The patent makes the FEC padding bits and reserved bits multi-functional by using them for both their original error correction purposes and for transmitting signal parameters. This universal usage of existing bits enables efficient communication of control information while maintaining the original error correction functionality, resolving the contradiction between communication efficiency and information completeness
2Loss of information
If separate communication channels are added for parameter transmission, then complete signal parameter communication is achieved, but system complexity increases
Solution Approach 1:
The patent merges the function of signal parameter transmission with the existing data communication channel by embedding control information in FEC padding bits and reserved bits. This consolidation eliminates the need for separate communication channels, reducing system complexity while ensuring complete signal parameter communication between DSPs in mirrored links
3Productivity
If power levels are not precisely adjusted, then system operation is simpler, but overall performance and power consumption optimization are compromised
Solution Approach 1:
The patent implements feedback mechanisms by transmitting power adjustment information and calibration data through the embedded control channels. The DSPs exchange performance metrics and adjust power levels based on received feedback, enabling precise power optimization while maintaining manageable system complexity through automated control loops
Data Source
AI summary
A system may include a first link including a first digital signal processor (DSP), a first optical receiver, and a first optical transmitter. The system may include a second link including a second DSP, a second optical receiver, and a second optical transmitter. The second DSP may be coupled to the first DSP using one or more of an active electrical cable or an active optical cable. The second DSP may communicate with the first DSP using one or more forward error correction (FEC) padding bits or one or more reserved bits.