Boolean Circuit Protection via Variable Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for protecting electronic circuits against hardware Trojans are either expensive, complex, or lack provability, with existing prevention and detection techniques failing to provide comprehensive and efficient solutions for ensuring the integrity of electronic components during manufacturing, particularly in scenarios where malicious modifications can occur.
Innovation Solution
A Boolean circuit protection method that modifies the structural description of electronic circuits by encoding variables with random numbers at each clock event, using a combination of binary codes and additional codes to create a protected variable that prevents unauthorized access and detects faults injected by malicious circuits, thereby thwarting Trojan horse insertion and detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reactive detection methods are used to detect Trojan horses, then Trojan horse insertion can be detected, but false positives and false negatives occur and detection reliability is difficult to quantify
Solution Approach 1:
The patent applies preliminary action by embedding protection circuits and integrity verification mechanisms into the circuit design before manufacturing. This proactive approach establishes trust anchors and cryptographic verification structures in advance, allowing the circuit to self-verify its integrity without relying on post-manufacturing detection that suffers from false positives and negatives.
Solution Approach 2:
The patent implements feedback through continuous integrity verification mechanisms that monitor circuit behavior and compare it against expected cryptographic signatures. This feedback loop enables real-time detection of modifications with quantifiable reliability, eliminating the uncertainty of reactive detection methods.
2Reliability
If proactive prevention methods are used to prevent Trojan horse insertion, then Trojan horse insertion can be prevented, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by transforming the prevention approach from physical security measures to cryptographic parameter verification. Instead of complex physical tamper-proofing, the circuit uses cryptographic signatures and integrity checks to prevent Trojan insertion, reducing manufacturing complexity while maintaining high prevention effectiveness.
Solution Approach 2:
The patent introduces cryptographic intermediaries (trust anchors, verification circuits, and integrity signatures) that mediate between the manufacturing process and the final product security. These intermediaries provide a standardized, manageable layer of protection that reduces overall system complexity compared to direct physical security measures.
3Reliability
If reverse engineering is used to check component integrity, then Trojan horses can be detected, but the process is particularly long and complex for circuits with several million gates
Solution Approach 1:
The patent extracts the integrity verification function from complex reverse engineering processes and implements it as embedded protection circuits within the design itself. This extraction allows verification to occur through simple cryptographic checks rather than time-consuming manual reverse engineering, dramatically reducing verification time while maintaining reliability.
Solution Approach 2:
The patent substitutes mechanical reverse engineering processes with cryptographic verification mechanisms. Instead of physically analyzing and dissecting circuits with millions of gates, the system uses mathematical cryptography for rapid integrity verification, replacing a slow mechanical process with a fast computational one.
4Measurement precision
If logic testing with scan chains is used to detect Trojans, then verification functionality can be implemented, but the circuit requires additional logic gates and increased complexity
Solution Approach 1:
The patent applies universality by designing protection circuits that serve multiple functions: they provide cryptographic verification, prevent Trojan insertion, and enable integrity monitoring all within a unified circuit structure. This multi-functionality reduces overall complexity compared to separate detection mechanisms like scan chains.
Solution Approach 2:
The patent merges the protection functionality directly into the circuit logic itself, combining verification and prevention functions with the operational logic. This integration eliminates the need for separate scan chain structures and reduces overall circuit complexity while maintaining detection capability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The invention proposes a method for protecting a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by a bit, the method comprising the steps of: - selecting a set of k elementary Boolean variables of the circuit according to predefined selection criteria, - constructing a variable x represented by k bits by concatenation of the k selected variables, according to a chosen order, - determining a binary code C, comprising a set of code words and belonging to a given vector space, and the supplementary code D of the binary code C, according to a condition relating to the dual distance of the supplementary code D, the binary code C having a length n and a size 2k, where k denotes the number of bits representing the variable x;- substitute the variable x in the structural description of the boolean circuit by a protected variable z represented by n bits such that: - any write operation on the variable x in the circuit is substituted by a write operation on the variable z, the variable z being generated by adding the variable x encoded by said code C to a random bit vector y encoded by the supplementary code D, and - any read operation of the variable x in the circuit is substituted by an operation of reading the value of the protected variable z and an operation of decoding said value read from the protected variable z using a decoding matrix J of size (n × k) determined from the binary code C and the supplementary code D of the binary code C.;