Optimizing Boolean Logic via Karnaugh Map Array Indexing
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Solution Overview
Problem
Existing digital circuit design methods using Boolean logic often result in inefficiencies due to redundancies and unnecessary inputs in Boolean expressions, leading to increased power consumption and complexity in digital circuits.
Innovation Solution
The system optimizes Boolean logic by generating a one-dimensional array to determine locations within a Karnaugh map, searching for simplified minterms and implicants, and using the Quine-McCluskey algorithm to remove duplicative variables, thereby reducing the number of logic gates and inputs required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional Boolean logic design methods are used, then digital circuits can be implemented, but redundancies and unnecessary inputs increase power consumption and circuit complexity
Solution Approach 1:
The patent extracts and removes redundant terms and unnecessary input variables from Boolean expressions through systematic analysis. The method identifies and eliminates duplicative elements in the logic expression, keeping only the essential terms needed to achieve the desired circuit functionality, thereby reducing both complexity and power consumption
Solution Approach 2:
The patent changes the parameters of the Boolean expression by transforming it into an optimized form with fewer terms and variables. This parameter transformation reduces the number of logic gates required and eliminates unnecessary inputs, directly addressing the contradiction between circuit complexity and power consumption
2Ease of manufacture
If Boolean expressions with repeating terms and unnecessary inputs are used, then the digital circuit can be implemented, but the number of logic gates and area increase
Solution Approach 1:
The method extracts and removes redundant terms from the Boolean expression, identifying and eliminating duplicative elements. This extraction process reduces the number of logic gates needed while maintaining the circuit's functional requirements, thereby reducing the semiconductor substrate area without compromising ease of manufacture
Solution Approach 2:
The patent discards unnecessary input variables and repeating terms that do not contribute to the desired circuit output. By eliminating these redundant elements, the method reduces the number of logic gates required, directly decreasing the area needed on the semiconductor substrate while preserving the essential functionality
3Productivity
If software tools use traditional algorithms to manipulate Boolean expressions, then optimization can be achieved, but the process is computationally intensive and time-consuming
Solution Approach 1:
The patent applies preliminary analysis techniques to identify redundant terms and unnecessary variables before full optimization processing. By performing preliminary identification of duplicative elements, the method reduces the computational burden of subsequent optimization steps, thereby increasing productivity while reducing computation time
Solution Approach 2:
The optimization process is segmented into distinct phases: preliminary identification of redundancies, systematic elimination of redundant terms, and final optimization. This segmentation allows each phase to be optimized independently, improving overall computational efficiency and reducing total optimization time while maintaining high productivity
Data Source
AI summary
Systems and methods for optimizing Boolean logic are provided. The systems generate a one-dimensional array having a plurality of values corresponding to a plurality of indices, and determine a first location of a Karnaugh map in a first dimension thereof. The first location is determined using a first value of the one-dimensional array corresponding to a first index of the one-dimensional array. The systems also determine a second location of the Karnaugh map in a second dimension thereof. The second location is determined using a second value of the one-dimensional array corresponding to a second index of the one-dimensional array. The systems evaluate a target location within the Karnaugh map corresponding to the first and second indices in the first and second dimensions of the Karnaugh map, respectively, and search for at least one of a simplified minterm and a simplified implicant having the target location using the one-dimensional array.