Boolean Resynthesis for IC Optimization via Filtering
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Solution Overview
Problem
Current Boolean resynthesis techniques for integrated circuit optimization are limited by high computational complexity, which restricts their scalability and applicability in electronic design automation due to the need for computationally expensive methods like truth tables and BDDs.
Innovation Solution
The implementation of a theory of Boolean filtering, a weaker notion of maximum set of permissible functions computed via truth tables, a parallel package for truth table computation, and a generalized refactoring engine to support multiple representation forms, combined with a practical Boolean resynthesis flow that reduces the number of gates processed and retains optimization opportunities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Boolean resynthesis techniques are used to improve optimization opportunities, then the quality of results is improved, but the computational cost and runtime increase significantly
Solution Approach 1:
The patent divides the logic circuit into multiple windows or regions, applying Boolean resynthesis selectively to each window rather than to the entire circuit. This segmentation allows the computational complexity to be distributed and managed in smaller, more tractable units, reducing the overall computational burden while maintaining optimization quality.
Solution Approach 2:
The patent performs preliminary analysis to identify candidate windows and pre-compute necessary information (such as fanin/fanout cones and don't care conditions) before applying Boolean resynthesis. This preliminary preparation reduces the computational work required during the actual resynthesis phase by having critical data ready in advance.
2Measurement precision
If complete functional properties are gathered using truth tables and BDDs, then Boolean resynthesis accuracy is improved, but scalability is limited due to computational expense
Solution Approach 1:
The patent computes functional properties partially by focusing only on the specific windows selected for resynthesis rather than computing complete properties for the entire circuit. This partial computation approach gathers sufficient functional information for the targeted regions without the excessive computational cost of analyzing the whole circuit, thereby improving scalability.
Solution Approach 2:
The patent applies different levels of analysis depth to different regions of the circuit based on their optimization potential. High-priority windows receive complete functional property analysis, while other regions receive lighter analysis or are skipped entirely. This local differentiation maintains accuracy where needed while improving overall scalability.
Data Source
AI summary
Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.