Boost Capacitor Structure for High-Resolution Display Devices
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Solution Overview
Problem
In organic light emitting display devices, the large area occupied by capacitors due to their structure limits the implementation of high resolution, as increasing the conductor area and reducing the distance between conductors to maintain capacitance results in increased pixel size.
Innovation Solution
The display device design includes a polycrystalline semiconductor layer with a driving transistor, a boost capacitor structure that reduces the distance between conductors, allowing for a smaller capacitor area while maintaining capacitance, by using a boost capacitor with a lower and upper boost electrode and an oxide semiconductor layer, and a connection electrode to connect the gate electrode and boost electrode, enabling efficient pixel layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the conductor is increased to secure high capacitance, then the capacitance is improved, but the area occupied by the capacitor in one pixel increases, making it difficult to implement high resolution
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by placing the lower boost electrode on the first gate insulating layer and the upper boost electrode on the oxide semiconductor layer, utilizing vertical stacking to increase capacitance without expanding pixel area
Solution Approach 2:
The capacitor structure is nested within the existing transistor layers, with the lower boost electrode integrated into the first gate insulating layer and the upper boost electrode integrated into the oxide semiconductor layer, allowing the capacitor to occupy space within the vertical profile of the transistor rather than requiring additional lateral space
2Area of stationary object
If the distance between conductors is reduced to maintain capacitance, then the capacitor area is reduced, but the manufacturing precision and structural stability may be compromised
Solution Approach 1:
By moving to a three-dimensional stacked configuration, the patent increases the effective capacitance through vertical separation distance while maintaining reasonable lateral dimensions, thus achieving high capacitance in a compact area without requiring extremely small conductor spacing that would be difficult to manufacture
Solution Approach 2:
The patent changes the geometric parameters of the capacitor by introducing vertical stacking with insulating layers, increasing the effective surface area of the electrodes while maintaining manufacturable distances between conductors, thereby achieving high capacitance without compromising manufacturing precision
Data Source
AI summary
A display device includes: a substrate; a polycrystalline semiconductor layer which includes a first electrode, a channel, and a second electrode of a driving transistor disposed on the substrate; a first gate insulating layer disposed on the polycrystalline semiconductor layer; a gate electrode of the driving transistor which is disposed on the first gate insulating layer and overlaps the channel; a lower first scan line disposed on the first gate insulating layer; a second gate insulating layer disposed on the gate electrode and on the lower first scan line; a first lower boost electrode disposed on the second gate insulating layer; a first interlayer-insulating layer disposed on the first lower boost electrode; an oxide semiconductor layer disposed on the first interlayer-insulating layer and including a first upper boost electrode overlapping the first lower boost electrode; and a first connection electrode connecting the gate electrode and the first upper boost electrode.