Boost Capacitor Circuit Area Efficiency via Voltage Doubler
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Solution Overview
Problem
Conventional boost capacitor circuits in charge pumps have low area efficiency due to their inability to accumulate a sufficient charge on each unit area, limiting the generation of high voltages required for data programming and erasing in flash memory devices.
Innovation Solution
A boost capacitor circuit design incorporating a first nMOS transistor and a voltage doubler circuit with specific transistor configurations, including thick-gate-oxide nMOS and thin-gate-oxide pMOS transistors, that increases the voltage at a second node to provide a boosted voltage with expanded amplitude, enhancing area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional boost capacitor circuits operate with voltage amplitude equal to working voltage VDD, then the circuit structure is simple, but the area efficiency is low due to limited charge accumulation
Solution Approach 1:
The patent changes the voltage amplitude parameter from VDD to 2×VDD by introducing a voltage doubler circuit. This parameter change enables the boost capacitor to accumulate twice the charge per unit area (2×C×VDD instead of C×VDD), directly resolving the contradiction between charge accumulation and capacitor area.
Solution Approach 2:
The voltage doubler circuit acts as an intermediary component that converts the working voltage VDD into a doubled voltage 2×VDD. This intermediary mechanism enables the boost capacitor to operate at higher voltage amplitude without requiring larger capacitor area, thus improving area efficiency.
2Quantity of substance
If the voltage amplitude is increased to improve area efficiency, then charge accumulation per unit area increases, but the circuit complexity increases due to additional transistors
Solution Approach 1:
The patent segments the voltage boosting function into two separate modules: the voltage doubler circuit (using pMOS transistors) and the boost capacitor circuit (using nMOS transistors). This segmentation allows each module to be optimized independently, achieving 2×VDD voltage amplitude while maintaining clear functional separation and manageable circuit complexity.
Solution Approach 2:
The voltage doubler circuit serves multiple functions: it doubles the voltage amplitude, provides the boosted voltage to the boost capacitor, and enables the charge pump to achieve higher area efficiency. This multi-functionality reduces the need for additional dedicated components, thereby controlling overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved design significantly increases area efficiency by allowing the accumulation of a higher charge on each unit area, effectively raising the output voltage and enhancing the charge pump's ability to generate the required high voltages for flash memory operations.
Implementation Method 1
the voltage at the second node is raised by the voltage doubler circuit so that the first nMOS transistor can provide a boosted voltage at its gate with expanded amplitude
Implementation Method 2
the first nMOS transistor having a gate for providing a boosted voltage
Data Source
AI summary
A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.