Boost Circuit Parasitic Diode Control
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Solution Overview
Problem
Conventional boost circuits face inefficiencies in power conversion and size constraints due to significant voltage drops and the need for large rectifying devices, which affect battery life in portable equipment.
Innovation Solution
A novel boost circuit design incorporating a NMOS switching device, a PMOS rectifying device, and control transistors with a controller to manage their operations, minimizing voltage drops and device size through complementary switching and parasitic diode configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a diode is used as a rectifying device in a boost circuit, then the circuit structure is simple, but the voltage drop is large resulting in low power conversion efficiency
Solution Approach 1:
The patent changes the rectifying device from a diode to a PMOS transistor, altering the electrical parameters of the circuit. The PMOS transistor has a much smaller on-resistance compared to the forward voltage drop of a diode, thereby reducing power loss and improving conversion efficiency while maintaining reasonable circuit complexity
Solution Approach 2:
The patent uses the parasitic diode inherent in the PMOS transistor structure to achieve rectification function, eliminating the need for a separate rectifying diode. This copying of the rectification function from an external component to an intrinsic device property simplifies the overall circuit structure
2Loss of energy
If a PMOS transistor is used as a rectifying device, then power conversion efficiency is improved, but the substrate gate connection creates a parasitic diode that causes continuous power supply in suspend mode
Solution Approach 1:
The patent divides the substrate gate control into two independent paths: one path controls the main rectification function during normal operation, while the other path controls the suspend mode through a separate switch. This segmentation allows independent optimization of each function without interference
Solution Approach 2:
The patent introduces a control switch as an intermediary between the substrate gate and the output terminal. This intermediary component enables precise control of the parasitic diode's conduction state, allowing the circuit to properly suspend power supply when required while maintaining the efficiency benefits of the PMOS transistor
3Reliability
If two rectifying devices are used to prevent overload current, then protection is improved, but the device size increases and power conversion efficiency decreases
Solution Approach 1:
The patent makes the PMOS transistor serve multiple functions: it acts as the main rectifying device during normal operation, provides overload protection through its controlled conduction, and enables suspend mode control. This multi-functionality eliminates the need for separate protection components, reducing overall device size while maintaining reliability
Solution Approach 2:
The PMOS transistor's inherent characteristics and controlled operation allow it to protect itself and the circuit from overload conditions. The device automatically limits current through its on-resistance and can be controlled to block current in abnormal conditions, providing self-protection without requiring additional dedicated protection components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances power conversion efficiency and reduces device size, preventing input voltage output during suspend modes without compromising efficiency, thus improving battery life and reducing manufacturing costs.
Implementation Method 1
electric energy is stored in the inductor L101 while the switching device M101 is on. When the switching device M101 is off, the electric energy stored in the inductor L101 is output by being added with an input voltage Vin
Implementation Method 2
The parasitic diode D102 is formed between a node of the inductor L101 side of the PMOS transistor M102 and the substrate gate of the PMOS transistor M102. An anode of the parasitic diode D102 is wired to the node of the inductor L101 side of the PMOS transistor M102, and a cathode of the parasitic diode D102 is wired to the node of the output terminal OUT side of the PMOS transistor M102
Data Source
AI summary
This patent specification describes a boost circuit which includes an inductor wired to an input terminal, a switching device connected between the inductor and a ground, a rectifying device formed of a MOS transistor and connected between the inductor and an output terminal and configured to be switched in accordance with the control signal, a first transistor wired to the input terminal and to a substrate gate of the rectifying device, a second transistor wired to the substrate gate of the rectifying device and to the output terminal and a controller configured to control each operation of the switching device, the rectifying device and the first and second transistors so that the first transistor is off and the second transistor is on in a boost mode and the first transistor is on and the second transistor is off in a boost suspend mode.