Boost Converter Clock Synchronization With Programmable Frequency Limits

Solution Overview

Problem

Boost converters in systems like envelope tracking for RF power amplifiers require synchronized clock signals with frequencies within specific ranges to optimize voltage boosting, but existing methods generate multiple independent clocks, increasing complexity and inefficiency.

Innovation Solution

The technique synchronizes the boost clock with the buck clock by using a minimum and maximum frequency limiting block to adjust the boost clock frequency, ensuring it falls within optimal ranges for the boost converter's operation without needing an independent boost clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple independent clock signals are generated for boost and buck converters, then each converter can operate at its optimized frequency, but the system complexity increases

Engineering Contradiction:

Improveoptimized converter operationVSAvoidmultiple independent clocks

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the boost clock and buck clock generation into a single synchronized clock system. The boost clock is derived from the buck clock through a frequency divider that divides the buck clock frequency by a programmable factor N, ensuring both converters share a common clock reference while maintaining the boost clock within its required frequency range for stable operation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic frequency adjustment by making the division factor N programmable. This allows the boost clock frequency to be dynamically adjusted based on operating conditions, ensuring it remains within the stable frequency range while adapting to different load and voltage requirements, thus resolving the contradiction between fixed frequency optimization and system flexibility.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If the boost clock frequency is synchronized to the buck clock, then system complexity is reduced, but the boost clock frequency may fall outside the optimal range

Engineering Contradiction:

Improvesynchronized clock systemVSAvoidboost converter stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic frequency adjustment by making the division factor N programmable. This allows the boost clock frequency to be dynamically adjusted based on operating conditions, ensuring it remains within the stable frequency range while adapting to different load and voltage requirements, thus resolving the contradiction between fixed frequency optimization and system flexibility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the frequency parameter of the boost clock by dividing the buck clock frequency by a programmable factor N. This parameter adjustment ensures the boost clock frequency falls within the required range [f_min, f_max] for stable boost converter operation, preventing under-boosting and over-boosting issues while maintaining synchronization with the buck clock.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the boost clock frequency is limited to a predetermined range, then converter stability is improved, but frequency flexibility is reduced

Engineering Contradiction:

Improveconverter stabilityVSAvoidfrequency range

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic frequency adjustment by making the division factor N programmable. This allows the boost clock frequency to be dynamically adjusted based on operating conditions, ensuring it remains within the stable frequency range while adapting to different load and voltage requirements, thus resolving the contradiction between fixed frequency optimization and system flexibility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent creates a universal clock generation system where a single buck clock source serves multiple functions: it directly clocks the buck converter and, through a programmable frequency divider, generates the boost clock. This multi-functional approach allows the system to maintain stability within the predetermined frequency range while adapting to different operating conditions through programmable division ratios.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP3985854B1Programmable frequency range for boost converter clocks

Publication Date: 2023.08.23 QUALCOMM INC

AI summary

Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst / T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking / delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.